PEF 20954 HT V1.1 Infineon Technologies, PEF 20954 HT V1.1 Datasheet - Page 36

• Manufacturer Part Number: PEF 20954 HT V1.1
• Description: IC ECHO CANCELLER DGTL TQFP144
• Manufacturer: Infineon Technologies

Specifications of PEF 20954 HT V1.1

• Function: Smart Integrated Digital Echo Canceller (SIDEC)
• Interface: PCM, Serial, UCC
• Number Of Circuits: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 350mA
• Power (watts): 900mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Double Talk Detection
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: PEF20954HTV1.1; SP000007505

Table 19
Ball No. Symbol
N10
P10
N1
P1
Table 20
Ball No. Symbol
J13
K14
G13
G14
Data Sheet
UPRES
UPRES
DISWD
UPRESI
SI
RI
SO
RO
Processor Watchdog Circuit
Speech Highways
I/O, PU/PD Function
I/O, PU/PD Function
O
O
I, PU
I, PU
I, PD
I, PD
O
O
write predefined values to the registers WDG1
to WDG3 in this sequence within 2 s and
DISWD='1'. Also active if PORES='0' or
UPRESI='0'
Same as UPRES, but low active
Disable of P-Reset on active watchdog
condition if set to low
Produces a reset signal at UPRES, UPRES if
set to low
2.048 Mbit/s Send speech highway input. Start
of timeslot 0, bit 7 can be flexibly aligned to the
SYNCI/SYNCO pulse in 122 ns steps via
registers SIALIGN and PHALIGN[3:2]
2.048 Mbit/s Receive speech highway input.
Start of timeslot 0, bit 7 can be flexibly aligned
to the SYNCI/SYNCO pulse in 122 ns steps via
registers RIALIGN and PHALIGN[1:0]
2.048 Mbit/s Send speech highway output.
Start of timeslot 0, bit 7 can be flexibly aligned
to the SYNCI/SYNCO pulse in 122 ns steps via
registers SOALIGN and PHALIGN[5:4]
2.048 Mbit/s Receive speech highway output.
This signal will has a fixed delay of one PCM
frame (125 s) with respect to RI
P-Reset. High pulse (125 s) if the P fails to
36
Rev. 2, 2004-07-28
Pin Description
PEB 20954
PEF 20954