PEF 20954 HT V1.1 Infineon Technologies, PEF 20954 HT V1.1 Datasheet - Page 7

• Manufacturer Part Number: PEF 20954 HT V1.1
• Description: IC ECHO CANCELLER DGTL TQFP144
• Manufacturer: Infineon Technologies

Specifications of PEF 20954 HT V1.1

• Function: Smart Integrated Digital Echo Canceller (SIDEC)
• Interface: PCM, Serial, UCC
• Number Of Circuits: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 350mA
• Power (watts): 900mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Double Talk Detection
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: PEF20954HTV1.1; SP000007505

List of Figures
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Data Sheet
Logic Symbol of the SIDEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
SIDEC in a Circuit Emulation Service Carried over ATM. . . . . . . . . . . 16
SIDEC in a Voice over IP Gateway . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SIDEC in a Private Branch Exchange (PBX) . . . . . . . . . . . . . . . . . . . . 18
SIDEC in a Wireless System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Pin Configuration P-TQFP-144-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Pin Configuration P-LFBGA-160-2(top view) . . . . . . . . . . . . . . . . . . . . 21
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Explanation of Options for A- and m-Law Conversion . . . . . . . . . . . . . 48
Bypass and Disabling Functions of the SIDEC . . . . . . . . . . . . . . . . . . 49
UCC Signal for control of PCM Signal . . . . . . . . . . . . . . . . . . . . . . . . . 50
Internet Working Unit: SIDEC between a FALC and IWE8 . . . . . . . . . 51
Master Clock Mode, ext. 32.768 MHz, no SDECI Clock . . . . . . . . . . . 52
Master Clock Mode with External 8.192 MHz Clock . . . . . . . . . . . . . . 53
Slave Clock Mode with External 8.192 MHz and 32.768 MHz. . . . . . . 54
Reference Clock Mode with 2.048 MHz. . . . . . . . . . . . . . . . . . . . . . . . 55
128 ms Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Multiple SIDEC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
PCM Signal Timing and Frame Alignment . . . . . . . . . . . . . . . . . . . . . . 58
Delay of PCM Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
PCM and UCC Signal synhcronization to SCLKI and SYNCI . . . . . . . 59
Timing of SYNCI and SYNCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Clock Timing within External VCO Capture Range . . . . . . . . . . . . . . . 61
Serial Interface (Controlling and Monitoring) Timing . . . . . . . . . . . . . . 62
UCC Interface Signal Timing and Frame Alignment . . . . . . . . . . . . . . 63
Special Cases for Multiframe Alignment and Timing Characteristics. . 65
Timing of Supporting signals for CAS-BR Applications . . . . . . . . . . . . 66
Explanation of Test Pattern Generation (random sign signal) . . . . . . 100
Input/Output Waveforms for AC-Tests. . . . . . . . . . . . . . . . . . . . . . . . 130
Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
PCM Signal Timing and Frame Alignment . . . . . . . . . . . . . . . . . . . . . 134
Delay of PCM Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
PCM and UCC Signal synchronization to SCLKI and SYNCI . . . . . . 135
Timing of SYNCI and SYNCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Clock Timing within External VCO Capture Range . . . . . . . . . . . . . . 139
Serial Interface (Controlling and Monitoring) Timing . . . . . . . . . . . . . 140
UCC Interface Signal Timing and Frame Alignment . . . . . . . . . . . . . 142
Special Cases for Multiframe Alignment and Timing Characteristics. 144
Timing of Supporting signals for CAS-BR Applications . . . . . . . . . . . 146
Internal Read Signal and Internal Write Signal . . . . . . . . . . . . . . . . . 147
Read Timing in Multiplexed Intel Mode (IM0='0', IM1='0') . . . . . . . . . 148
Write Timing in Multiplexed Intel Mode (IM0='0', IM1='0') . . . . . . . . . 148
7
Rev. 2, 2004-07-28
PEB 20954
PEF 20954
Page