PEF 20954 HT V1.1 Infineon Technologies, PEF 20954 HT V1.1 Datasheet - Page 97

• Manufacturer Part Number: PEF 20954 HT V1.1
• Description: IC ECHO CANCELLER DGTL TQFP144
• Manufacturer: Infineon Technologies

Specifications of PEF 20954 HT V1.1

• Function: Smart Integrated Digital Echo Canceller (SIDEC)
• Interface: PCM, Serial, UCC
• Number Of Circuits: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 350mA
• Power (watts): 900mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Double Talk Detection
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: PEF20954HTV1.1; SP000007505

UCCFRS[4:0]
*Caution: The activation of the bit 128FRSEN is solely intended for a configuration where
only one SIDEC in 128 ms mode is used for one PCM30 interface processing only 16
channels. If two SIDECs in 128 ms master and slave mode are used in parallel for one
PCM interface the activation of this bit could result in severe damage of the external
driver at the UCCO bus.
WRUCC[5:0] (Addr.: 63H): Write/Read UCCI, Reset value = 00H
WRORAM
ARAM [4:0]
DORAM[7:0] (Addr.: 64H): Data Output RAM, Reset value = 00H
DORAM [7:0]
IMASKFRS[7:0] (Addr.: 65H): Interrupt Mask for the special UCC frame FRS,
IMASKFRS[7:0]
Note: In 128 ms mode the change of an unmasked bit generates an interrupt condition
only if the frame number of the special UCC frame corresponds to one of the 16
processed channels or bit UCCFRS.128FRSEN is set to '1'.
Data Sheet
Reset value = 00H
RAM[7]
IMASK
FRS[7]
DO
-
RAM[6]
IMASK
FRS[6]
DO
-
'1': Write access: the byte stored in register DORAM is written to the
Each activated (set to '1') mask bit prevents the generation of an
'0': disables the output of all frames at UCCO and the activation of
Denotes the frame number of the special UCC frame FRS.
'0': read access: the byte stored in the UCC input RAM (IRAM) at
Value corresponds to the ORAM or IRAM address where data is
written to or read from
Data to be written to the ORAM at address WRUCC. ARAM [4:0]
UCC interrupt at a change of the corresponding bit in FRS.
TUCCO for all frames in 128 ms mode if the number
does not correspond to one of the 16 processed channels.*
UCC output RAM (ORAM) at UCC frame number ARAM [4:0].
UCC frame number ARAM [4:0] is copied to register DIRAM.
Data can be read after 8 CLK32 cycles.
RAM[5]
IMASK
FRS[5]
WRO
RAM
DO
ARAM[4] ARAM[3] ARAM[2] ARAM[1] ARAM[0]
RAM[5]
IMASK
FRS[4]
DO
97
RAM[3]
IMASK
FRS[3]
DO
RAM[2]
IMASK
FRS[2]
DO
Register Description
RAM[1]
IMASK
FRS[1]
DO
Rev. 2, 2004-07-28
PEB 20954
PEF 20954
RAM[0]
IMASK
FRS[0]
DO