PEF 20954 HT V1.1 Infineon Technologies, PEF 20954 HT V1.1 Datasheet - Page 51

• Manufacturer Part Number: PEF 20954 HT V1.1
• Description: IC ECHO CANCELLER DGTL TQFP144
• Manufacturer: Infineon Technologies

Specifications of PEF 20954 HT V1.1

• Function: Smart Integrated Digital Echo Canceller (SIDEC)
• Interface: PCM, Serial, UCC
• Number Of Circuits: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 350mA
• Power (watts): 900mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Double Talk Detection
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: PEF20954HTV1.1; SP000007505

4
4.1
Figure 12
to an interworking element IC.
The SIDEC is used to cancel the echo on the side of the FALC 56 which is the near end
in this case. There are two INFINEON products in this Inter working unit connected to
the SIDEC. The FALC serves as a frame and line interface component whereas the
IWE8 PEB 4220 operates as an interworking element. For multiframe alignment in the
IWE8, FRMFBX must have a correct timing relation to FRDATX. For this purpose the
SIDEC adjusts the delay from the TMFBI input to the TMFBO output to the delay of the
SI input to the SO output. For the support of the CAS-BR transparency the SIDEC
passes the robbed bits that are indicated by the FALC via the TSIGM input directly
through to the SO output by overwriting the computed value of the robbed bit with the
value of the SI input.
Figure 12
Data Sheet
FALC56
Synchronization Pulse Transmit
Synchronization Pulse Receive
Receive Multiframe Begin
System Clock 8.192 MHz
Receive Data Out (RDO)
Transmit Data In (XDI)
System Clock Transmit
Receive Signal Marker
System Clock Receive
Frame SYNC (FSC)
illustrates an example for the pin connection of the SIDEC to an E1/T1 IC and
Operational Description
Pin Connection Diagram for SIDEC
Internet Working Unit: SIDEC between a FALC and IWE8
(SCLKX)
(RSIGM)
(SCLKR)
(CLK8M)
(RMFB)
(SYPR)
(SYPX)
8 kHz
8.192 MHz
TMFBI
TSIGM
RO
SYNCI
SI
SCLKI
SIDEC
51
CTRL32
32.768 MHz
VCO
TMFBO
CLK32
SO
RI
Operational Description
InterworkingIWE8 & FALC56 & SIDEC
Framer Receive Multiframe
Begin (FRMFBO)
Framer Receive Data Input
(FRDATX)
Framer Transmit Data Output
(FTDATX)
Reference Clock for SYM
Mode (RFCLK)
Rev. 2, 2004-07-28
PEB 20954
PEF 20954
IWE8