SAM3S1B Atmel Corporation, SAM3S1B Datasheet

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SAM3S1B

Manufacturer Part Number
SAM3S1B
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM3S1B

Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
64 MHz
Cpu
Cortex-M3
# Of Touch Channels
23
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
10
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Features
Core
Pin-to-pin compatible with AT91SAM7S legacy products (48- and 64-pin versions)
Memories
System
Low Power Modes
Peripherals
I/O
Packages
– ARM
– Memory Protection Unit (MPU)
– Thumb
– From 64 to 256 Kbytes embedded Flash, 128-bit wide access, memory accelerator,
– From 16 to 48 Kbytes embedded SRAM
– 16 Kbytes ROM with embedded bootloader routines (UART, USB) and IAP routines
– 8-bit Static Memory Controller (SMC): SRAM, PSRAM, NOR and NAND Flash
– Memory Protection Unit (MPU)
– Embedded voltage regulator for single supply operation
– Power-on-Reset (POR), Brown-out Detector (BOD) and Watchdog for safe
– Quartz or ceramic resonator oscillators: 3 to 20 MHz main power with Failure
– High precision 8/12 MHz factory trimmed internal RC oscillator with 4 MHz default
– Slow Clock Internal RC oscillator as permanent low-power mode device clock
– Two PLLs up to 130 MHz for device clock and for USB
– Temperature Sensor
– Up to 22 peripheral DMA (PDC) channels
– Sleep and Backup modes, down to 3 µA in Backup mode
– Ultra low power RTC
– USB 2.0 Device: 12 Mbps, 2668 byte FIFO, up to 8 bidirectional Endpoints. On-Chip
– Up to 2 USARTs with ISO7816, IrDA
– Two 2-wire UARTs
– Up to 2 Two Wire Interface (I2C compatible), 1 SPI, 1 Serial Synchronous Controller
– Up to 6 Three-Channel 16-bit Timer/Counter with capture, waveform, compare and
– 4-channel 16-bit PWM with Complementary Output, Fault Input, 12-bit Dead Time
– 32-bit Real-time Timer and RTC with calendar and alarm features
– Up to 15-channel, 1Msps ADC with differential input mode and programmable gain
– One 2-channel 12-bit 1Msps DAC
– One Analog Comparator with flexible input selection, Selectable input hysteresis
– 32-bit Cyclic Redundancy Check Calculation Unit (CRCCU)
– Up to 79 I/O lines with external interrupt capability (edge or level sensitivity),
– Three 32-bit Parallel Input/Output Controllers, Peripheral DMA assisted Parallel
– 100-lead LQFP, 14 x 14 mm, pitch 0.5 mm/100-ball LFBGA, 9 x 9 mm, pitch 0.8 mm
– 64-lead LQFP, 10 x 10 mm, pitch 0.5 mm/64-pad QFN 9x9 mm, pitch 0.5 mm
– 48-lead LQFP, 7 x 7 mm, pitch 0.5 mm/48-pad QFN 7x7 mm, pitch 0.5 mm
single plane
support
operation
Detection and optional low power 32.768 kHz for RTC or device clock
frequency for device startup. In-application trimming access for frequency
adjustment
Transceiver
(I2S), 1 High Speed Multimedia Card Interface (SDIO/SD Card/MMC)
PWM mode. Quadrature Decoder Logic and 2-bit Gray Up/Down Counter for
Stepper Motor
Generator Counter for Motor Control
stage
debouncing, glitch filtering and on-die Series Resistor Termination
Capture Mode
®
Cortex
®
-2 instruction set
®
-M3 revision 2.0 running at up to 64 MHz
®
, RS-485, SPI, Manchester and Modem Mode
AT91SAM
ARM-based
Flash MCU
SAM3S Series
6500C–ATARM–8-Feb-11

SAM3S1B Summary of contents

Page 1

Features • Core ® ® – ARM Cortex -M3 revision 2.0 running MHz – Memory Protection Unit (MPU) ® – Thumb -2 instruction set • Pin-to-pin compatible with AT91SAM7S legacy products (48- and 64-pin versions) • ...

Page 2

... Kbytes SAM3S2B 32 Kbytes single plane 128 Kbytes SAM3S2A 32 Kbytes single plane 64 Kbytes SAM3S1C 16 Kbytes single plane 64 Kbytes SAM3S1B 16 Kbytes single plane 64 Kbytes SAM3S1A 16 Kbytes single plane Notes: 1. Full Modem support on USART1. 2. One channel is reserved for internal temperature sensor. SAM3S 2 Timer ...

Page 3

SAM3S Block Diagram Figure 2-1. SAM3S 100-pin Version Block Diagram System Controller T ST PCK0-PCK2 PLLA PMC PLLB RC 12/8/4 M 3-20 MHz XIN Osc. X OUT SUPC XIN32 OSC 32k X OUT32 RC 32k ERASE 8 GPBREG RTT ...

Page 4

Figure 2-2. SAM3S 64-pin Version Block Diagram System Controller T ST PCK0-PCK2 PLLA PMC PLLB RC 12/8/4 M 3-20 MHz XIN Osc. XOUT SUPC XIN32 OSC 32K XOUT32 RC 32k ERASE 8 GPBREG RTT VDDIO RTC VDDCORE POR VDDPLL RSTC ...

Page 5

Figure 2-3. SAM3S 48-pin Version Block Diagram System Controller TST PCK0-PCK2 PLLA PMC PLLB RC 12/8/4 M XIN 3-20 MHz XOUT Osc. SUPC XIN32 OSC 32K XOUT32 RC 32k ERASE 8 GPBREG RTT VDDIO RTC VDDCORE POR VDDPLL RSTC WDT ...

Page 6

Signal Description Table 3-1 Table 3-1. Signal Description List Signal Name Function Peripherals I/O Lines and USB transceiver VDDIO Power Supply Voltage Regulator Input, ADC, DAC and VDDIN Analog Comparator Power Supply VDDOUT Voltage Regulator Output VDDPLL Oscillator and ...

Page 7

Table 3-1. Signal Description List (Continued) Signal Name Function URXDx UART Receive Data UTXDx UART Transmit Data PA0 - PA31 Parallel IO Controller A PB0 - PB14 Parallel IO Controller B PC0 - PC31 Parallel IO Controller C PIODC0-PIODC7 Parallel ...

Page 8

Table 3-1. Signal Description List (Continued) Signal Name Function TD SSC Transmit Data RD SSC Receive Data TK SSC Transmit Clock RK SSC Receive Clock TF SSC Transmit Frame Sync RF SSC Receive Frame Sync TCLKx TC Channel x External ...

Page 9

Table 3-1. Signal Description List (Continued) Signal Name Function PGMEN0-PGMEN2 Programming Enabling PGMM0-PGMM3 Programming Mode PGMD0-PGMD15 Programming Data PGMRDY Programming Ready PGMNVALID Data Direction PGMNOE Programming Read PGMCK Programming Clock PGMNCMD Programming Command DDM USB Full Speed Data - DDP ...

Page 10

Package and Pinout 4.1 SAM3S4/2/1C Package and Pinout Figure 4-2 4.1.1 100-lead LQFP Package Outline Figure 4-1. 4.1.2 100-ball LFBGA Package Outline The 100-Ball LFBGA package has a 0.8 mm ball pitch and respects Green Standards. Its dimen- sions ...

Page 11

LQFP Pinout Table 4-1. 100-lead LQFP SAM3S4/2/1C Pinout 1 ADVREF 2 GND 3 PB0/AD4 4 PC29/AD13 5 PB1/AD5 6 PC30/AD14 7 PB2/AD6 8 PC31 9 PB3/AD7 10 VDDIN 11 VDDOUT 12 PA17/PGMD5/AD0 13 PC26 14 PA18/PGMD6/AD1 15 PA21/PGMD9/AD8 ...

Page 12

LFBGA Pinout Table 4-2. 100-ball LFBGA SAM3S4/2/1C Pinout A1 PB1/AD5 C6 A2 PC29 C7 A3 VDDIO C8 A4 PB9/PGMCK/XIN C9 A5 PB8/XOUT C10 A6 PB13/DAC0 D1 A7 DDP/PB11 D2 A8 DDM/PB10 D3 A9 TMS/SWDIO/PB6 D4 A10 JTAGSEL D5 ...

Page 13

SAM3S4/2/1B Package and Pinout Figure 4-3. Figure 4-4. 6500C–ATARM–8-Feb-11 Orientation of the 64-pad QFN Package TOP VIEW Orientation of the 64-lead LQFP Package SAM3S ...

Page 14

LQFP and QFN Pinout 64-pin version SAM3S devices are pin-to-pin compatible with AT91SAM7S legacy products. Furthermore, SAM3S products have new functionalities shown in italic in Table 4-3. 64-pin SAM3S4/2/1B Pinout 1 ADVREF 17 2 GND 18 3 PB0/AD4 ...

Page 15

SAM3S4/2/1A Package and Pinout Figure 4-5. Figure 4-6. 6500C–ATARM–8-Feb-11 Orientation of the 48-pad QFN Package TOP VIEW Orientation of the 48-lead LQFP Package SAM3S ...

Page 16

LQFP and QFN Pinout Table 4-4. 48-pin SAM3S4/2/1A Pinout 1 ADVREF 13 2 GND 14 3 PB0/AD4 15 4 PB1/AD5 16 5 PB2/AD6 17 6 PB3/AD7 18 7 VDDIN 19 8 VDDOUT 20 9 PA17/PGMD5/AD0 21 10 PA18/PGMD6/AD1 ...

Page 17

Power Considerations 5.1 Power Supplies The SAM3S product has several types of power supply pins: • VDDCORE pins: Power the core, the embedded memories and the peripherals; voltage ranges from 1.62V to 1.95V. • VDDIO pins: Power the Peripherals ...

Page 18

Figure 5-1. Note: Figure 5-2. Note: Figure 5-3 Since the PIO state is preserved when in backup mode, any free PIO line can be used to switch off the external regulator by driving the PIO line at low level (PIO ...

Page 19

Figure 5-3. 5.4 Active Mode Active mode is the normal running mode with the core clock running from the fast RC oscillator, the main crystal oscillator or the PLLA. The power management controller can be used to adapt the frequency ...

Page 20

WKUPEN0-15 pins (level transition, configurable debouncing) • Supply Monitor alarm • RTC alarm • RTT alarm 5.5.2 Wait Mode The purpose of the wait mode is to achieve very low power consumption while maintaining the whole device in a ...

Page 21

Low Power Mode Summary Table The modes detailed above are the main low power modes. Each part can be set off sep- arately and wake up sources can be individually configured. of the configurations of the ...

Page 22

Wake-up Sources The wake-up events allow the device to exit the backup mode. When a wake-up event is detected, the Supply Controller performs a sequence which automatically reenables the core power supply and the SRAM power supply, if they ...

Page 23

Fast Startup The SAM3S allows the processor to restart in a few microseconds while the processor is in wait mode or in sleep mode. A fast start up can occur upon detection of a low level on one of ...

Page 24

Input/Output Lines The SAM3S has several kinds of input/output (I/O) lines such as general purpose I/Os (GPIO) and system I/Os. GPIOs can have alternate functionality due to multiplexing capabilities of the PIO controllers. The same PIO line can be ...

Page 25

Table 6-1. System I/O Configuration Pin List. SYSTEM_IO Default function bit number after reset 12 ERASE 10 DDM 11 DDP 7 TCK/SWCLK 6 TMS/SWDIO 5 TDO/TRACESWO 4 TDI - PA7 - PA8 - PB9 - PB8 Notes PB12 ...

Page 26

Test Pin The TST pin is used for JTAG Boundary Scan Manufacturing Test or Fast Flash programming mode of the SAM3S series. The TST pin integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it ...

Page 27

Memories 7.1 Product Mapping Figure 7-1. SAM3S Product Mapping Code 0x00000000 Boot Memory 0x00400000 1 MByte 1 MByte Internal Flash 0x00800000 Internal ROM 0x00C00000 Reserved 0x1FFFFFFF External RAM 0x60000000 SMC Chip Select 0 0x61000000 SMC Chip Select 1 0x62000000 ...

Page 28

Embedded Memories 7.2.1 Internal SRAM The ATSAM3S4 product (256-Kbyte internal Flash version) embeds a total of 48 Kbytes high- speed SRAM. The ATSAM3S2 product (128-Kbyte internal Flash version) embeds a total of 32 Kbytes high- speed SRAM. The ATSAM3S1 ...

Page 29

Flash Speed The user needs to set the number of wait states depending on the frequency used. For more details, refer to the “AC Characteristics” sub section in the product “Electrical Charac- teristics” Section. 7.2.3.5 Lock Regions Several lock ...

Page 30

Fast Flash Programming Interface The Fast Flash Programming Interface allows programming the device through either a serial JTAG interface or through a multiplexed fully-handshaked parallel port. It allows gang program- ming with market-standard industrial programmers. The FFPI supports read, ...

Page 31

See the system controller block diagram in 6500C–ATARM–8-Feb-11 Figure 8-1 on page 32 SAM3S 31 ...

Page 32

Figure 8-1. System Controller Block Diagram VDDIO Zero-Power Power-on Reset Supply Monitor (Backup) WKUP0 - WKUP15 General Purpose Backup Registers SLCK SLCK XIN32 Xtal 32 kHz Oscillator XOUT32 Embedded 32 kHz RC Oscillator Backup Power Supply NRST FSTT0 - FSTT15 ...

Page 33

System Controller and Peripherals Mapping Please refer to All the peripherals are in the bit band region and are mapped in the bit band alias region. 8.2 Power-on-Reset, Brownout and Supply Monitor The SAM3S embeds three features to monitor, ...

Page 34

Peripherals 9.1 Peripheral Identifiers Table 9-1 the control of the peripheral interrupt with the Nested Vectored Interrupt Controller and for the control of the peripheral clock with the Power Management Controller. Table 9-1. Peripheral Identifiers Instance ID Instance Name ...

Page 35

APB/AHB bridge The SAM3S product embeds one peripheral bridge: The peripherals of the bridge are clocked by MCK. 9.3 Peripheral Signal Multiplexing on I/O Lines The SAM3S product features 2 PIO controllers on 48-pin and 64-pin versions (PIOA, PIOB) ...

Page 36

PIO Controller A Multiplexing Table 9-2. Multiplexing on PIO Controller A (PIOA) I/O Line Peripheral A Peripheral B PA0 PWMH0 TIOA0 PA1 PWMH1 TIOB0 PA2 PWMH2 SCK0 PA3 TWD0 NPCS3 PA4 TWCK0 TCLK0 PA5 RXD0 NPCS3 PA6 TXD0 PCK0 ...

Page 37

PIO Controller B Multiplexing Table 9-3. Multiplexing on PIO Controller B (PIOB) I/O Line Peripheral A Peripheral B PB0 PWMH0 PB1 PWMH1 PB2 URXD1 PB3 UTXD1 PB4 TWD1 PB5 TWCK1 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PWML1 PB13 ...

Page 38

PIO Controller C Multiplexing Table 9-4. Multiplexing on PIO Controller C (PIOC) I/O Line Peripheral A Peripheral B PC0 D0 PC1 D1 PC2 D2 PC3 D3 PC4 D4 PC5 D5 PC6 D6 PC7 D7 PC8 NWE PC9 NANDOE PC10 ...

Page 39

ARM Cortex M3 Processor 10.1 About this section This section provides the information required for application and system-level software devel- opment. It does not provide information on debug components, features, or operation. This material is for microcontroller software ...

Page 40

Figure 10-1. Typical Cortex-M3 implementation The ...

Page 41

System level interface The Cortex-M3 processor provides multiple interfaces using AMBA speed, low latency memory accesses. It supports unaligned data accesses and implements atomic bit manipulation that enables faster peripheral controls, system spinlocks and thread-safe Boolean data handling. The ...

Page 42

System timer The system timer, SysTick 24-bit count-down timer. Use this as a Real Time Operating Sys- tem (RTOS) tick timer simple counter. 10.3.4.4 Memory protection unit The Memory protection unit (MPU) improves system ...

Page 43

The proces- sor implements two stacks, the main stack and the process stack, with independent copies of the stack pointer, see In Thread mode, the CONTROL ...

Page 44

Table 10-2. Name R0-R12 MSP PSP LR PC PSR ASPR IPSR EPSR PRIMASK FAULTMASK BASEPRI CONTROL 1. 2. 10.4.3.1 General-purpose registers R0-R12 are 32-bit general-purpose registers for data operations. 10.4.3.2 Stack Pointer The Stack Pointer (SP) is register R13. In ...

Page 45

Program Status Register The Program Status Register (PSR) combines: • Application Program Status Register (APSR) • Interrupt Program Status Register (IPSR) • Execution Program Status Register (EPSR). These registers are mutually exclusive bitfields in the 32-bit PSR. The bit ...

Page 46

The PSR bit assignments are Access these registers individually combination of any two or all three registers, using the register name as an argument to the MSR ...

Page 47

C Carry or borrow flag add operation did not result in a carry bit or subtract operation resulted in a borrow bit 1 = add operation resulted in a carry bit or subtract operation did not result ...

Page 48

Execution Program Status Register The EPSR contains the Thumb state bit, and the execution state bits for either the: • If-Then (IT) instruction • Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction. See the ...

Page 49

Priority Mask Register The PRIMASK register prevents activation of all exceptions with configurable priority. See the register summary • PRIMASK effect 1 = prevents the activation of ...

Page 50

Base Priority Mask Register The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is set to a nonzero value, it prevents the activation of all exceptions with same or lower priority level as the BASEPRI value. ...

Page 51

CONTROL register The CONTROL register controls the stack used and the privilege level for software execution when the processor is in Thread mode. See the register summary in its attributes. The bit assignments are ...

Page 52

Exceptions and interrupts The Cortex-M3 processor supports interrupts and system exceptions. The processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception changes the normal flow of software control. The processor uses handler mode ...

Page 53

CMSIS mapping of the Cortex-M3 NVIC registers” on page 151 • “NVIC programming hints” on page 6500C–ATARM–8-Feb-11 163. SAM3S 53 ...

Page 54

Memory model This section describes the processor memory map, the behavior of memory accesses, and the bit-banding features. The processor has a fixed memory map that provides up to 4GB of addressable memory. The memory map is: The regions ...

Page 55

Normal The processor can re-order transactions for efficiency, or perform speculative reads. 10.5.1.2 Device The processor preserves transaction order relative to other transactions to Device or Strongly- ordered memory. 10.5.1.3 Strongly-ordered The processor preserves transaction order relative to all ...

Page 56

Means that accesses are observed in program order, that is always observed before A2. 10.5.3 Behavior of memory accesses The behavior of accesses to each region in the memory map is: Table 10-4. Address range 0x00000000- 0x1FFFFFFF ...

Page 57

Table 10-5. Address range 0x60000000- 0x7FFFFFFF 0x80000000- 0x9FFFFFFF 0xA0000000- 0xBFFFFFFF 0xC0000000- 0xDFFFFFFF 0xE0000000- 0xE00FFFFF 0xE0100000- 0xFFFFFFFF 1. 2. 10.5.4 Software ordering of memory accesses The order of instructions in the program flow does not always guarantee the order of the ...

Page 58

Use an ISB instruction to ensure the new MPU setting takes effect immediately after • Vector table. If the program changes an entry in the vector table, and then enables the corresponding exception, use a DMB instruction between the ...

Page 59

Table 10-7. Address range 0x40000000- 0x400FFFFF 0x42000000- 0x43FFFFFF A word access to the SRAM or peripheral bit-band alias regions map to a single bit in the SRAM or peripheral bit-band region. The following formula shows how the alias region maps ...

Page 60

Figure 10-2. Bit-band mapping 0x23FFFFFC 0x2200001C 7 7 10.5.5.1 Directly accessing an alias region Writing to a word in the alias region updates a single bit in the bit-band region. Bit[0] of the value written to a word in the ...

Page 61

Little-endian format In little-endian format, the processor stores the least significant byte of a word at the lowest- numbered byte, and the most significant byte at the highest-numbered byte. For example: Address A A+1 A+2 A+3 10.5.7 Synchronization primitives ...

Page 62

No write was performed. This indicates that the value returned the first step might be out of date. The software must retry the read-modify-write sequence, Software can use the synchronization primitives to implement a semaphores as follows: • Use ...

Page 63

Exception model This section describes the exception model. 10.6.1 Exception states Each exception is in one of the following states: 10.6.1.1 Inactive The exception is not active and not pending. 10.6.1.2 Pending The exception is waiting to be serviced ...

Page 64

Memory management fault A memory management fault is an exception that occurs because of a memory protection related fault. The MPU or the fixed memory protection constraints determines this fault, for both instruction and data memory transactions. This fault ...

Page 65

Interrupt (IRQ) A interrupt, or IRQ exception signalled by a peripheral, or generated by a software request. All interrupts are asynchronous to instruction execution. In the system, peripherals use interrupts to communicate with the processor. Table 10-9. ...

Page 66

Clear-enable Registers” on page For more information about hard faults, memory management faults, bus faults, and usage faults, see 10.6.3 Exception handlers The processor handles exceptions using: 10.6.3.1 Interrupt Service Routines (ISRs) Interrupts IRQ0 to IRQ34 are the ...

Page 67

Figure 10-3. Vector table On system reset, the vector table is fixed at address 0x00000000. Privileged software can write to the VTOR to relocate the vector table start address to a different memory location, in the range 0x00000080 to 0x3FFFFF80, ...

Page 68

Configurable priority values are in the range 0-15. This means that the Reset, Hard fault, and NMI exceptions, with fixed negative priority values, always have higher priority than any other exception. For example, assigning a higher priority value to IRQ[0] ...

Page 69

Tail-chaining This mechanism speeds up exception servicing. On completion of an exception handler, if there is a pending exception that meets the requirements for exception entry, the stack pop is skipped and control transfers to the new exception handler. ...

Page 70

If no higher priority exception occurs during exception entry, the processor starts executing the exception handler and automatically changes the status of the corresponding pending interrupt to active. If another higher priority exception occurs during exception entry, the processor starts ...

Page 71

BX instruction • attempting to execute an instruction from a memory region marked as Non-Executable • an MPU fault because of a privilege ...

Page 72

Usually, the exception priority, together with the values of the exception mask registers, deter- mines whether the processor enters the fault handler, and whether a fault handler can preempt another fault handler. as described in In some situations, a fault ...

Page 73

Power management The Cortex-M3 processor sleep modes reduce power consumption: • Backup Mode • Wait Mode • Sleep Mode The SLEEPDEEP bit of the SCR selects which sleep mode is used, see ter” on page Modes” in the PMC ...

Page 74

PRIMASK to zero. For more information about PRIMASK and FAULT- MASK see 10.8.2.2 Wakeup from WFE The processor wakes up if: • it detects an exception with sufficient priority to cause exception entry In addition, if ...

Page 75

Instruction set summary The processor implements a version of the Thumb instruction set. ported instructions. In Table • angle brackets, <>, enclose alternative forms of the operand • braces, {}, enclose optional operands • the Operands column is not ...

Page 76

Table 10-13. Cortex-M3 instructions (Continued) Mnemonic ISB IT LDM LDMDB, LDMEA LDMFD, LDMIA LDR LDRB, LDRBT LDRD LDREX LDREXB LDREXH LDRH, LDRHT LDRSB, LDRSBT LDRSH, LDRSHT LDRT LSL, LSLS LSR, LSRS MLA MLS MOV, MOVS MOVT MOVW, MOV MRS MSR ...

Page 77

Table 10-13. Cortex-M3 instructions (Continued) Mnemonic RBIT REV REV16 REVSH ROR, RORS RRX, RRXS RSB, RSBS SBC, SBCS SBFX SDIV SEV SMLAL SMULL SSAT STM STMDB, STMEA STMFD, STMIA STR STRB, STRBT STRD STREX STREXB STREXH STRH, STRHT STRT SUB, ...

Page 78

Table 10-13. Cortex-M3 instructions (Continued) Mnemonic TEQ TST UBFX UDIV UMLAL UMULL USAT UXTB UXTH WFE WFI 10.10 Intrinsic functions ANSI cannot directly access some Cortex-M3 instructions. This section describes intrinsic func- tions that can generate these instructions, provided by ...

Page 79

The CMSIS also provides a number of functions for accessing the special registers using MRS and MSR instructions: Table 10-15. CMSIS intrinsic functions to access the special registers Special register PRIMASK FAULTMASK BASEPRI CONTROL MSP PSP 10.11 About the instruction ...

Page 80

Bit[0] of any address you write to the PC with a BX, BLX, LDM, LDR, or POP instruction must be 1 for correct execution, because this bit indicates the required instruction set, and the Cortex-M3 processor only supports Thumb instructions. ...

Page 81

LSR #n ROR #n RRX - If you omit the shift, or specify LSL #0, the instruction uses the value in Rm. If you specify a shift, the shift is applied to the value in Rm, and the resulting 32-bit ...

Page 82

LSR Logical shift right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n places, into the right-hand 32-n bits of the result. And it sets the left-hand n bits of the ...

Page 83

ROR Rotate right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n places, into the right-hand 32-n bits of the result. And it moves the right-hand n bits of the register ...

Page 84

All other load and store instructions generate a usage fault exception if they perform an unaligned access, and therefore their accesses must be address aligned. For more information about usage faults see Unaligned accesses are usually slower than aligned accesses. ...

Page 85

This section describes: • “The condition flags” • “Condition code suffixes” 10.11.7.1 The condition flags The APSR contains the following condition flags For more information about the APSR see A carry occurs: • if the result ...

Page 86

Table 10-16. Condition code suffixes (Continued) Suffix 10.11.7.3 Absolute value The example below shows the use of a conditional instruction to find the absolute value of a number ABS(R1). MOVS ...

Page 87

Memory access instructions Table 10-17 Table 10-17. Memory access instructions Mnemonic ADR CLREX LDM{mode} LDR{type} LDR{type} LDR{type}T LDR LDREX{type} POP PUSH STM{mode} STR{type} STR{type} STR{type}T STREX{type} 6500C–ATARM–8-Feb-11 shows the memory access instructions: Brief description Load PC-relative address Clear Exclusive ...

Page 88

ADR Load PC-relative address. 10.12.1.1 Syntax ADR{cond} Rd, label where: cond Rd label 10.12.1.2 Operation ADR determines the address by adding an immediate value to the PC, and writes the result to the destination register. ADR produces position-independent code, ...

Page 89

LDR and STR, immediate offset Load and Store with immediate offset, pre-indexed immediate offset, or post-indexed immediate offset. 10.12.2.1 Syntax op{type}{cond} Rt, [Rn {, #offset}] op{type}{cond} Rt, [Rn, #offset]! op{type}{cond} Rt, [Rn], #offset opD{cond} Rt, Rt2, [Rn {, #offset}] ...

Page 90

Post-indexed addressing The address obtained from the register Rn is used as the address for the memory access. The offset value is added to or subtracted from the address, and written back into the register Rn. The ...

Page 91

Examples LDR R8, [R10] LDRNE R2, [R5, #960]! STR R2, [R9,#const-struc] STRH R3, [R4], #4 LDRD R8, R9, [R3, #0x20] STRD R0, R1, [R8], #-16 6500C–ATARM–8-Feb-11 ; Loads R8 from the address in R10. ; Loads (conditionally) R2 from ...

Page 92

LDR and STR, register offset Load and Store with register offset. 10.12.3.1 Syntax op{type}{cond} Rt, [Rn LSL #n}] where: op LDR STR type cond LSL #n 10.12.3.2 Operation LDR ...

Page 93

Condition flags These instructions do not change the flags. 10.12.3.5 Examples STR R0, [R5, R1] LDRSB R0, [R5, R1, LSL #1] ; Read byte value from an address equal to STR R0, [R1, R2, LSL #2] ; Stores R0 ...

Page 94

LDR and STR, unprivileged Load and Store with unprivileged access. 10.12.4.1 Syntax op{type}T{cond} Rt, [Rn {, #offset}] where: op LDR STR type is one of cond Rt Rn offset 10.12.4.2 Operation These load and ...

Page 95

LDR, PC-relative Load register from memory. 10.12.5.1 Syntax LDR{type}{cond} Rt, label LDRD{cond} Rt, Rt2, label where: type cond Rt Rt2 label 10.12.5.2 Operation LDR loads a register with a value from a PC-relative memory ...

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IT block. 10.12.5.4 Condition flags These ...

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LDM and STM Load and Store Multiple registers. 10.12.6.1 Syntax op{addr_mode}{cond} Rn{!}, reglist where: op LDM STM addr_mode IA DB cond present the final address, that is loaded from or stored to, is written ...

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The accesses happen in order of decreasing register numbers, with the highest numbered regis- ter using the highest memory address and the lowest number register using the lowest memory address. If the writeback suffix is specified, the value of Rn ...

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PUSH and POP Push registers onto, and pop registers off a full-descending stack. 10.12.7.1 Syntax PUSH{cond} reglist POP{cond} reglist where: cond reglist It must be comma separated if it contains more than one register or register range. PUSH and ...

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LDREX and STREX Load and Store Register Exclusive. 10.12.8.1 Syntax LDREX{cond} Rt, [Rn {, #offset}] STREX{cond} Rd, Rt, [Rn {, #offset}] LDREXB{cond} Rt, [Rn] STREXB{cond} Rd, Rt, [Rn] LDREXH{cond} Rt, [Rn] STREXH{cond} Rd, Rt, [Rn] where: cond Rd Rt ...

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Condition flags These instructions do not change the flags. 10.12.8.5 Examples MOV R1, #0x1 try LDREX R0, [LockAddr] CMP R0, #0 ITT EQ STREXEQ R0, R1, [LockAddr] CMPEQ R0, #0 BNE try .... 6500C–ATARM–8-Feb-11 ; Initialize the ‘lock taken’ ...

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CLREX Clear Exclusive. 10.12.9.1 Syntax CLREX{cond} where: cond 10.12.9.2 Operation Use CLREX to make the next STREX, STREXB, or STREXH instruction write 1 to its destination register and fail to perform the store useful in exception handler ...

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General data processing instructions Table 10-20 Table 10-20. Data processing instructions Mnemonic ADC ADD ADDW AND ASR BIC CLZ CMN CMP EOR LSL LSR MOV MOVT MOVW MVN ORN ORR RBIT REV REV16 REVSH ROR 6500C–ATARM–8-Feb-11 shows the data ...

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Table 10-20. Data processing instructions (Continued) Mnemonic RRX RSB SBC SUB SUBW TEQ TST SAM3S 104 Brief description Rotate Right with Extend Reverse Subtract Subtract with Carry Subtract Subtract Test Equivalence Test See “ASR, LSL, LSR, ROR, and RRX” on ...

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ADD, ADC, SUB, SBC, and RSB Add, Add with carry, Subtract, Subtract with carry, and Reverse Subtract. 10.13.1.1 Syntax op{S}{cond} {Rd,} Rn, Operand2 op{cond} {Rd,} Rn, #imm12 where: op ADD ADC SUB SBC RSB S result of the operation, ...

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Rd can be SP only in ADD and SUB, and only with the additional restrictions: – Rn must also be SP – any shift in Operand2 must be limited to a maximum of 3 bits using LSL • Rn ...

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Multiword arithmetic examples 10.13.1.7 64-bit addition The example below shows two instructions that add a 64-bit integer contained in R2 and R3 to another 64-bit integer con- tained in R0 and R1, and place the result in R4 and ...

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AND, ORR, EOR, BIC, and ORN Logical AND, OR, Exclusive OR, Bit Clear, and OR NOT. 10.13.2.1 Syntax op{S}{cond} {Rd,} Rn, Operand2 where: op AND ORR EOR BIC ORN S result of the operation, see cond Rd Rn Operand2 ...

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Examples AND R9, R2, #0xFF00 ORREQ R2, R0, R5 ANDS R9, R8, #0x19 EORS R7, R11, #0x18181818 BIC R0, R1, #0xab ORN R7, R11, R14, ROR #4 ORNS R7, R11, R14, ASR #32 6500C–ATARM–8-Feb-11 SAM3S 109 ...

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ASR, LSL, LSR, ROR, and RRX Arithmetic Shift Right, Logical Shift Left, Logical Shift Right, Rotate Right, and Rotate Right with Extend. 10.13.3.1 Syntax op{S}{cond} Rd, Rm, Rs op{S}{cond} Rd, Rm, #n RRX{S}{cond} Rd, Rm where: op ASR LSL ...

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C flag is updated to the last bit shifted out, except when the shift length is 0, see Operations” on page 10.13.3.5 Examples ASR R7, R8 Arithmetic shift right by 9 bits LSLS R1, R2, #3 ...

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CLZ Count Leading Zeros. 10.13.4.1 Syntax CLZ{cond} Rd, Rm where: cond Rd Rm 10.13.4.2 Operation The CLZ instruction counts the number of leading zeros in the value in Rm and returns the result in Rd. The result value is ...

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CMP and CMN Compare and Compare Negative. 10.13.5.1 Syntax CMP{cond} Rn, Operand2 CMN{cond} Rn, Operand2 where: cond Rn Operand2 details of the options. 10.13.5.2 Operation These instructions compare the value in a register with Operand2. They update the condition ...

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MOV and MVN Move and Move NOT. 10.13.6.1 Syntax MOV{S}{cond} Rd, Operand2 MOV{cond} Rd, #imm16 MVN{S}{cond} Rd, Operand2 where: S result of the operation, see cond Rd Operand2 details of the options. imm16 10.13.6.2 Operation The MOV instruction copies ...

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PC is ignored • a branch occurs to the address created by forcing bit[0] of that value to 0. Though it is possible to use MOV as a branch instruction, ARM strongly ...

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MOVT Move Top. 10.13.7.1 Syntax MOVT{cond} Rd, #imm16 where: cond Rd imm16 10.13.7.2 Operation MOVT writes a 16-bit immediate value, imm16, to the top halfword, Rd[31:16], of its destination register. The write does not affect Rd[15:0]. The MOV, MOVT ...

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REV, REV16, REVSH, and RBIT Reverse bytes and Reverse bits. 10.13.8.1 Syntax op{cond} Rd, Rn where: op REV REV16 Reverse byte order in each halfword independently. REVSH Reverse byte order in the bottom halfword, and sign extend to 32 ...

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TST and TEQ Test bits and Test Equivalence. 10.13.9.1 Syntax TST{cond} Rn, Operand2 TEQ{cond} Rn, Operand2 where: cond Rn Operand2 details of the options. 10.13.9.2 Operation These instructions test the value in a register against Operand2. They update the ...

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Multiply and divide instructions Table 10-21 Table 10-21. Multiply and divide instructions Mnemonic MLA MLS MUL SDIV SMLAL SMULL UDIV UMLAL UMULL 6500C–ATARM–8-Feb-11 shows the multiply and divide instructions: Brief description Multiply with Accumulate, 32-bit result Multiply and Subtract, ...

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MUL, MLA, and MLS Multiply, Multiply with Accumulate, and Multiply with Subtract, using 32-bit operands, and pro- ducing a 32-bit result. 10.14.1.1 Syntax MUL{S}{cond} {Rd,} Rn Multiply MLA{cond} Rd, Rn, Rm, Ra MLS{cond} Rd, Rn, Rm, Ra ...

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UMULL, UMLAL, SMULL, and SMLAL Signed and Unsigned Long Multiply, with optional Accumulate, using 32-bit operands and pro- ducing a 64-bit result. 10.14.2.1 Syntax op{cond} RdLo, RdHi, Rn, Rm where: op UMULL Unsigned Long Multiply. UMLAL Unsigned Long Multiply, ...

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SDIV and UDIV Signed Divide and Unsigned Divide. 10.14.3.1 Syntax SDIV{cond} {Rd,} Rn, Rm UDIV{cond} {Rd,} Rn, Rm where: cond 10.14.3.2 Operation SDIV performs a signed integer division of the value the value ...

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Saturating instructions This section describes the saturating instructions, SSAT and USAT. 10.15.1 SSAT and USAT Signed Saturate and Unsigned Saturate to any bit position, with optional shift before saturating. 10.15.1.1 Syntax op{cond} Rd, # shift #s} where: ...

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Restrictions Do not use SP and do not use PC 10.15.1.4 Condition flags These instructions do not affect the condition code flags. If saturation occurs, these instructions set the Q flag to 1. 10.15.1.5 Examples SSAT R7, #16, R7, ...

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Bitfield instructions Table 10-22 Table 10-22. Packing and unpacking instructions Mnemonic BFC BFI SBFX SXTB SXTH UBFX UXTB UXTH 6500C–ATARM–8-Feb-11 shows the instructions that operate on adjacent sets of bits in registers or bitfields: Brief description Bit Field Clear ...

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BFC and BFI Bit Field Clear and Bit Field Insert. 10.16.1.1 Syntax BFC{cond} Rd, #lsb, #width BFI{cond} Rd, Rn, #lsb, #width where: cond Rd Rn lsb width 10.16.1.2 Operation BFC clears a bitfield in a register. It clears width ...

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SBFX and UBFX Signed Bit Field Extract and Unsigned Bit Field Extract. 10.16.2.1 Syntax SBFX{cond} Rd, Rn, #lsb, #width UBFX{cond} Rd, Rn, #lsb, #width where: cond Rd Rn lsb width 10.16.2.2 Operation SBFX extracts a bitfield from one register, ...

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SXT and UXT Sign extend and Zero extend. 10.16.3.1 Syntax SXTextend{cond} {Rd ROR #n} UXTextend{cond} {Rd ROR #n} where: extend B H cond Rd Rm ROR #n ROR #8 Value from Rm is rotated right ...

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Branch and control instructions Table 10-23 Table 10-23. Branch and control instructions Mnemonic B BL BLX BX CBNZ CBZ IT TBB TBH 6500C–ATARM–8-Feb-11 shows the branch and control instructions: Brief description Branch Branch with Link Branch indirect with Link ...

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B, BL, BX, and BLX Branch instructions. 10.17.1.1 Syntax B{cond} label BL{cond} label BX{cond} Rm BLX{cond} Rm where BLX cond label but the address to branch to is created by changing bit[0] to ...

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PC in the BLX instruction • for BX and BLX, bit[ must be 1 for correct execution but a branch occurs to the target address created by changing bit[ • when any ...

Page 132

CBZ and CBNZ Compare and Branch on Zero, Compare and Branch on Non-Zero. 10.17.2.1 Syntax CBZ Rn, label CBNZ Rn, label where: Rn label 10.17.2.2 Operation Use the CBZ or CBNZ instructions to avoid changing the condition code flags ...

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IT If-Then condition instruction. 10.17.3.1 Syntax IT{x{y{z}}} cond where cond The condition switch for the second, third and fourth instruction in the IT block can be either possible to use AL (the ...

Page 134

PC must either be outside an IT block or must be the last instruction inside the IT block. These are: – ADD PC, PC, Rm – MOV PC, Rm – B, ...

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TBB and TBH Table Branch Byte and Table Branch Halfword. 10.17.4.1 Syntax TBB [Rn, Rm] TBH [Rn, Rm, LSL #1] where: Rn then the address of the table is the address of the byte immediately following the TBB or ...

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Examples ADR.W R0, BranchTable_Byte TBB [R0, R1] Case1 ; an instruction sequence follows Case2 ; an instruction sequence follows Case3 ; an instruction sequence follows BranchTable_Byte DCB 0 DCB ((Case2-Case1)/2) DCB ((Case3-Case1)/2) TBH [PC, R1, LSL #1] BranchTable_H DCI ...

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Miscellaneous instructions Table 10-25 Table 10-25. Miscellaneous instructions Mnemonic BKPT CPSID CPSIE DMB DSB ISB MRS MSR NOP SEV SVC WFE WFI 6500C–ATARM–8-Feb-11 shows the remaining Cortex-M3 instructions: Brief description Breakpoint Change Processor State, Disable Interrupts Change Processor State, ...

Page 138

BKPT Breakpoint. 10.18.1.1 Syntax BKPT #imm where: imm 10.18.1.2 Operation The BKPT instruction causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. imm ...

Page 139

CPS Change Processor State. 10.18.2.1 Syntax CPSeffect iflags where: effect IE ID iflags i f 10.18.2.2 Operation CPS changes the PRIMASK and FAULTMASK special register values. See registers” on page 48 10.18.2.3 Restrictions The restrictions are: • use CPS ...

Page 140

DMB Data Memory Barrier. 10.18.3.1 Syntax DMB{cond} where: cond 10.18.3.2 Operation DMB acts as a data memory barrier. It ensures that all explicit memory accesses that appear, in program order, before the DMB instruction are completed before any explicit ...

Page 141

DSB Data Synchronization Barrier. 10.18.4.1 Syntax DSB{cond} where: cond 10.18.4.2 Operation DSB acts as a special data synchronization memory barrier. Instructions that come after the DSB, in program order, do not execute until the DSB instruction completes. The DSB ...

Page 142

ISB Instruction Synchronization Barrier. 10.18.5.1 Syntax ISB{cond} where: cond 10.18.5.2 Operation ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor, so that all instructions following the ISB are fetched from memory again, after the ...

Page 143

MRS Move the contents of a special register to a general-purpose register. 10.18.6.1 Syntax MRS{cond} Rd, spec_reg where: cond Rd spec_reg PRIMASK, BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL. 10.18.6.2 Operation Use MRS in combination with MSR as part of a ...

Page 144

MSR Move the contents of a general-purpose register into the specified special register. 10.18.7.1 Syntax MSR{cond} spec_reg, Rn where: cond Rn spec_reg PRIMASK, BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL. 10.18.7.2 Operation The register access operation in MSR depends on the ...

Page 145

NOP No Operation. 10.18.8.1 Syntax NOP{cond} where: cond 10.18.8.2 Operation NOP does nothing. NOP is not necessarily a time-consuming NOP. The processor might remove it from the pipeline before it reaches the execution stage. Use NOP for padding, for ...

Page 146

SEV Send Event. 10.18.9.1 Syntax SEV{cond} where: cond 10.18.9.2 Operation SEV is a hint instruction that causes an event to be signaled to all processors within a multipro- cessor system. It also sets the local event register to 1, ...

Page 147

SVC Supervisor Call. 10.18.10.1 Syntax SVC{cond} #imm where: cond imm 10.18.10.2 Operation The SVC instruction causes the SVC exception. imm is ignored by the processor. If required, it can be retrieved by the exception handler to determine what service ...

Page 148

WFE Wait For Event. 10.18.11.1 Syntax WFE{cond} where: cond 10.18.11.2 Operation WFE is a hint instruction. If the event register is 0, WFE suspends execution until one of the following events occurs: • an exception, unless masked by the ...

Page 149

WFI Wait for Interrupt. 10.18.12.1 Syntax WFI{cond} where: cond 10.18.12.2 Operation WFI is a hint instruction that suspends execution until one of the following events occurs: • an exception • a Debug Entry request, regardless of whether Debug is ...

Page 150

About the Cortex-M3 The address map of the Private peripheral bus (PPB) is: Table 10-26. Core peripheral register regions Address 0xE000E008- 0xE000E00F 0xE000E010- 0xE000E01F 0xE000E100- 0xE000E4EF 0xE000ED00- 0xE000ED3F 0xE000ED90- 0xE000EDB8 0xE000EF00- 0xE000EF03 In register descriptions: • the register type ...

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Nested Vectored Interrupt Controller This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it uses. The NVIC supports: • interrupts. • A programmable priority level of 0-15 for each interrupt. A higher level ...

Page 152

Interrupt Priority Registers map to an array of 4-bit integers, so that the array IP[0] to IP[34] corresponds to the registers IPR0-IPR8, and the array entry IP[n] holds the interrupt priority for interrupt n. ...

Page 153

Interrupt Set-enable Registers The ISER0-ISER1 register enables interrupts, and show which interrupts are enabled. See: • the register summary in • Table 10-28 on page 152 The bit assignments are • ...

Page 154

Interrupt Clear-enable Registers The ICER0-ICER1 register disables interrupts, and shows which interrupts are enabled. See: • the register summary in • Table 10-28 on page 152 The bit assignments are • ...

Page 155

Interrupt Set-pending Registers The ISPR0-ISPR1 register forces interrupts into the pending state, and shows which interrupts are pending. See: • the register summary in • Table 10-28 on page 152 The bit assignments are ...

Page 156

Interrupt Clear-pending Registers The ICPR0-ICPR1 register removes the pending state from interrupts, and show which inter- rupts are pending. See: • the register summary in • Table 10-28 on page 152 The bit assignments are ...

Page 157

Interrupt Active Bit Registers The IABR0-IABR1 register indicates which interrupts are active. See: • the register summary in • Table 10-28 on page 152 The bit assignments are • ACTIVE Interrupt ...

Page 158

Interrupt Priority Registers The IPR0-IPR8 registers provide a 4-bit priority field for each interrupt (See the “Peripheral Iden- tifiers” section of the datasheet for more details). These registers are byte-accessible. See the register summary in fields, that map up ...

Page 159

IPR2 10.20.7.5 IPR1 10.20.7.6 IPR0 • Priority, byte offset 3 • Priority, byte offset 2 ...

Page 160

Find the IPR number and byte offset for interrupt N as follows: • the corresponding IPR number given DIV 4 • the byte offset of the required Priority field in this register is N ...

Page 161

Software Trigger Interrupt Register Write to the STIR to generate a Software Generated Interrupt (SGI). See the register summary in Table 10-27 on page 151 When the USERSETMPEND bit in the SCR is set to 1, unprivileged software can ...

Page 162

Level-sensitive interrupts The processor supports level-sensitive interrupts. A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal. Typ- ically this happens because the ISR accesses the peripheral, causing it to clear the interrupt request. When the ...

Page 163

NVIC design hints and tips Ensure software uses correctly aligned register accesses. The processor does not support unaligned accesses to NVIC registers. See the individual register descriptions for the supported access sizes. A interrupt can enter pending state even ...

Page 164

System control block The System control block (SCB) provides system implementation information, and system con- trol. This includes configuration, control, and reporting of the system exceptions. The system control block registers are: Table 10-30. Summary of the system control ...

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Auxiliary Control Register The ACTLR provides disable bits for the following processor functions: • IT folding • write buffer use for accesses to the default memory map • interruption of multi-cycle instructions. See the register summary in ments are: ...

Page 166

CPUID Base Register The CPUID register contains the processor part number, version, and implementation informa- tion. See the register summary in are Variant PartNo • Implementer Implementer code: 0x41 = ARM ...

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Interrupt Control and State Register The ICSR: • provides: – set-pending and clear-pending bits for the PendSV and SysTick exceptions • indicates: – the exception number of the exception being processed – whether there are preempted active exceptions – ...

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PENDSTSET RW SysTick exception set-pending bit. Write effect 1 = changes SysTick exception state to pending. Read SysTick exception is not pending 1 = SysTick exception is pending. • PENDSTCLR WO SysTick exception clear-pending ...

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RETTOBASE RO Indicates whether there are preempted active exceptions there are preempted active exceptions to execute 1 = there are no active exceptions, or the currently-executing exception is the only active exception. • VECTACTIVE RO Contains the ...

Page 170

Vector Table Offset Register The VTOR indicates the offset of the vector table base address from memory address 0x00000000. See the register summary in The bit assignments are Reserved TBLOFF • ...

Page 171

Application Interrupt and Reset Control Register The AIRCR provides priority grouping control for the exception model, endian status for data accesses, and reset control of the system. See the register summary in 164 and To write to this register, ...

Page 172

VECTCLRACTIVE WO Reserved for Debug use. This bit reads as 0. When writing to the register you must write 0 to this bit, otherwise behavior is Unpredictable. • VECTRESET WO Reserved for Debug use. This bit reads as 0. ...

Page 173

System Control Register The SCR controls features of entry to and exit from low power state. See the register summary in Table 10-30 on page 164 Reserved • SEVONPEND Send Event ...

Page 174

Configuration and Control Register The CCR controls entry to Thread mode and enables: • the handlers for hard fault and faults escalated by FAULTMASK to ignore bus faults • trapping of divide by zero and unaligned accesses • access ...

Page 175

If this bit is set unaligned access generates a usage fault. Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of whether UNALIGN_TRP is set to 1. • ...

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System Handler Priority Registers The SHPR1-SHPR3 registers set the priority level the exception handlers that have configurable priority. SHPR1-SHPR3 are byte accessible. See the register summary in their attributes. The system fault handlers and the ...

Page 177

System Handler Priority Register 1 The bit assignments are • PRI_7 Reserved • PRI_6 Priority of system handler 6, usage fault • PRI_5 Priority of system handler 5, bus fault • ...

Page 178

System Handler Priority Register 2 The bit assignments are • PRI_11 Priority of system handler 11, SVCall 10.21.9.3 System Handler Priority Register 3 The bit assignments are ...

Page 179

System Handler Control and State Register The SHCSR enables the system handlers, and indicates: • the pending status of the bus fault, memory management fault, and SVC exceptions • the active status of the system handlers. See the register ...

Page 180

MONITORACT Debug monitor active bit, reads Debug monitor is active • SVCALLACT SVC call active bit, reads SVC call is active • USGFAULTACT Usage fault exception active bit, reads exception ...

Page 181

Configurable Fault Status Register The CFSR indicates the cause of a memory management fault, bus fault, or usage fault. See the register summary The following subsections describe the subregisters that ...

Page 182

Memory Management Fault Status Register The flags in the MMFSR indicate the cause of memory access faults. The bit assignments are MMARVALID Reserved • MMARVALID Memory Management Fault Address Register (MMAR) valid flag value in ...

Page 183

Bus Fault Status Register The flags in the BFSR indicate the cause of a bus access fault. The bit assignments are BFRVALID Reserved • BFARVALID Bus Fault Address Register (BFAR) valid flag value in BFAR ...

Page 184

PRECISERR Precise data bus error precise data bus error data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault. When the ...

Page 185

Usage Fault Status Register The UFSR indicates the cause of a usage fault. The bit assignments are Reserved • DIVBYZERO Divide by zero usage fault divide by zero fault, or divide by ...

Page 186

When this bit is set to 1, the PC value stacked for the exception return points to the instruction that attempted the illegal use of the EPSR. This bit is not set undefined instruction uses the ...

Page 187

Hard Fault Status Register The HFSR gives information about events that activate the hard fault handler. See the register summary in This register is read, write to clear. This means that bits in the register read normally, but writing ...

Page 188

Memory Management Fault Address Register The MMFAR contains the address of the location that generated a memory management fault. See the register summary • ADDRESS When the MMARVALID bit of ...

Page 189

Bus Fault Address Register The BFAR contains the address of the location that generated a bus fault. See the register sum- mary • ADDRESS When the BFARVALID bit of the ...

Page 190

System control block design hints and tips Ensure software uses aligned accesses of the correct size to access the system control block registers: • except for the CFSR and SHPR1-SHPR3, it must use aligned word accesses • for the ...

Page 191

System timer, SysTick The processor has a 24-bit system timer, SysTick, that counts down from the reload value to zero, reloads (wraps to) the value in the LOAD register on the next clock edge, then counts down on subsequent ...

Page 192

SysTick Control and Status Register The SysTick CTRL register enables the SysTick features. See the register summary page 191 Reserved • COUNTFLAG Returns 1 if timer counted to ...

Page 193

SysTick Reload Value Register The LOAD register specifies the start value to load into the VAL register. See the register sum- mary • RELOAD Value to load into the VAL ...

Page 194

SysTick Current Value Register The VAL register contains the current value of the SysTick counter. See the register summary in Table 10-33 on page 191 • CURRENT Reads return the current ...

Page 195

SysTick Calibration Value Register The CALIB register indicates the SysTick calibration properties. See the register summary in Table 10-33 on page 191 31 30 NOREF SKEW • NOREF Reads as zero. • SKEW ...

Page 196

Memory protection unit This section describes the Memory protection unit (MPU). The MPU divides the memory map into a number of regions, and defines the location, size, access permissions, and memory attributes of each region. It supports: • independent ...

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Table 10-34. Memory attributes summary (Continued) Memory type Normal Use the MPU registers to define the MPU regions and their attributes. The MPU registers are: Table 10-35. MPU registers summary Address Name Type 0xE000ED90 TYPE RO 0xE000ED94 CTRL RW 0xE000ED98 ...

Page 198

MPU Type Register The TYPE register indicates whether the MPU is present, and if so, how many regions it sup- ports. See the register summary in assignments are • IREGION Indicates ...

Page 199

MPU Control Register The MPU CTRL register: • enables the MPU • enables the default memory map background region • enables use of the MPU when in the hard fault, Non-maskable Interrupt (NMI), and FAULTMASK escalated handlers. See the ...

Page 200

Any access by unprivileged software that does not address an enabled memory region causes a memory management fault. XN and Strongly-ordered rules always apply to the System Control Space regardless of the value of the ENABLE bit. When the ENABLE ...

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