SAM3S1B Atmel Corporation, SAM3S1B Datasheet - Page 71

• Manufacturer Part Number: SAM3S1B
• Manufacturer: Atmel Corporation

Specifications of SAM3S1B

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 64 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 23
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 10
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

10.7.1
10.7.2
6500C–ATARM–8-Feb-11
Fault types
Fault escalation and hard faults
Table 10-11
tus register, and the register bit that indicates that the fault has occurred. See
Fault Status Register” on page 181
Table 10-11. Faults
1.
2.
All faults exceptions except for hard fault have configurable exception priority, see
dler Priority Registers” on page
faults, see
Fault
Bus error on a vector read
Fault escalated to a hard fault
MPU mismatch:
Bus error:
Precise data bus error
Imprecise data bus error
Attempt to access a coprocessor
Undefined instruction
Attempt to enter an invalid instruction
set state
Invalid EXC_RETURN value
Illegal unaligned load or store
Divide By 0
• an internally-detected error such as an undefined instruction or an attempt to change state
• attempting to execute an instruction from a memory region marked as Non-Executable
• an MPU fault because of a privilege violation or an attempt to access an unmanaged region.
with a BX instruction
on instruction access
on data access
during exception stacking
during exception unstacking
during exception stacking
during exception unstacking
during instruction prefetch
Occurs on an access to an XN region even if the MPU is disabled.
Attempting to use an instruction set other than the Thumb instruction set.
(2)
“System Handler Control and State Register” on page
shows the types of fault, the handler used for the fault, the corresponding fault sta-
176. Software can disable execution of the handlers for these
for more information about the fault status registers.
Handler
Hard fault
Memory
managem
ent fault
Bus fault
Usage
fault
Bit name
VECTTBL
FORCED
-
IACCVIOL
DACCVIOL
MSTKERR
MUNSKERR
-
STKERR
UNSTKERR
IBUSERR
PRECISERR
IMPRECISER
R
NOCP
UNDEFINSTR
INVSTATE
INVPC
UNALIGNED
DIVBYZERO
(1)
179.
Fault status register
“Hard Fault Status
Register” on page 187
-
“Memory Management
Fault Address Register” on
page 188
-
“Bus Fault Status Register”
on page 183
“Usage Fault Status
Register” on page 185
“Configurable
SAM3S
“System Han-
(XN).
71