SAM3S1B Atmel Corporation, SAM3S1B Datasheet - Page 771

• Manufacturer Part Number: SAM3S1B
• Manufacturer: Atmel Corporation

Specifications of SAM3S1B

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 64 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 23
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 10
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

SAM3S
One of the POSEN or SPEEDEN bits must be also enabled.
• POSEN: POSition ENabled
0 = disable position.
1 = enables the position measure on channel 0 and 1
• SPEEDEN: SPEED ENabled
0 = disabled.
1 = enables the speed measure on channel 0, the time base being provided by channel 2.
• QDTRANS: Quadrature Decoding TRANSparent
0 = full quadrature decoding logic is active (direction change detected).
1 = quadrature decoding logic is inactive (direction change inactive) but input filtering and edge detection are performed.
• EDGPHA: EDGe on PHA count mode
0 = edges are detected on both PHA and PHB.
1 = edges are detected on PHA only.
• INVA: INVerted phA
0 = PHA (TIOA0) is directly driving quadrature decoder logic.
1 = PHA is inverted before driving quadrature decoder logic.
• INVB: INVerted phB
0 = PHB (TIOB0) is directly driving quadrature decoder logic.
1 = PHB is inverted before driving quadrature decoder logic.
• SWAP: SWAP PHA and PHB
0 = no swap between PHA and PHB.
1 = swap PHA and PHB internally, prior to driving quadrature decoder logic.
• INVIDX: INVerted InDeX
0 = IDX (TIOA1) is directly driving quadrature logic.
1 = IDX is inverted before driving quadrature logic.
• IDXPHB: InDeX pin is PHB pin
0 = IDX pin of the rotary sensor must drive TIOA1.
1 = IDX pin of the rotary sensor must drive TIOB0.
• FILTER:
0 = IDX,PHA, PHB input pins are not filtered.
1 = IDX,PHA, PHB input pins are filtered using MAXFILT value.
• MAXFILT: MAXimum FILTer
1.. 63: defines the filtering capabilities
Pulses with a period shorter than MAXFILT+1 MCK clock cycles are discarded.
771
6500C–ATARM–8-Feb-11