SAM3S1B Atmel Corporation, SAM3S1B Datasheet - Page 846

• Manufacturer Part Number: SAM3S1B
• Manufacturer: Atmel Corporation

Specifications of SAM3S1B

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 64 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 23
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 10
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

36.5.2
36.5.3
36.5.4
846
SAM3S
Power Management
Interrupt Sources
Fault Inputs
Table 36-2.
The PWM is not continuously clocked. The programmer must first enable the
Power Management Controller (PMC) before using the
not require PWM operations, the
later. In this case, the
In the
is connected.
The
rupt Controller (NVIC). Using the
Table 36-3.
The
mentation of these module within the product for detailed information about the fault generation
PWM
PWM
Instance
PWM
PWM
PWM
PWM
PWM
PWM
PWM
PWM
PWM
PWM
PWM
PWM
PWM
PWM
PWM
PWM
PWM
PWM
interrupt line is connected on one of the internal sources of the Nested Vectored Inter-
has the FAULT inputs connected to the different modules. Please refer to the imple-
description, Master Clock (MCK) is the clock of the peripheral bus to which the
I/O Lines (Continued)
Peripheral IDs
PWM
31
ID
will resume its operations where it left off.
PWM
PWM
PWMH3
PWML0
PWML0
PWML0
PWML0
PWML1
PWML1
PWML1
PWML1
PWML2
PWML2
PWML2
PWML2
PWML3
PWML3
PWML3
interrupt requires the NVIC to be programmed first.
clock can be stopped when not needed and be restarted
PWM
. However, if the application does
PC21
PC13
PB12
PC15
PB13
PC22
PA19
PA20
PA16
PA30
PA15
PB5
PC0
PC1
PC2
PC3
6500C–ATARM–8-Feb-11
PWM
clock in the
B
B
B
B
B
B
A
B
B
C
A
A
B
C
B
B
PWM