SAM3S1B Atmel Corporation, SAM3S1B Datasheet - Page 540
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SAM3S1B
Manufacturer Part Number
SAM3S1B
Description
Manufacturer
Atmel Corporation
Specifications of SAM3S1B
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
64 MHz
Cpu
Cortex-M3
# Of Touch Channels
23
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
10
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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29.7
Figure 29-3. SSC Functional Block Diagram
29.7.1
540
540
Functional Description
SAM3S
SAM3S
Clock Management
APB
MCK
Divider
Interface
Clock
User
This chapter contains the functional description of the following: SSC Functional Block, Clock
Management, Data format, Start, Transmitter, Receiver and Frame Sync.
The receiver and transmitter operate separately. However, they can work synchronously by pro-
gramming the receiver to use the transmit clock and/or to start a data transfer when transmission
starts. Alternatively, this can be done by programming the transmitter to use the receive clock
and/or to start a data transfer when reception starts. The transmitter and the receiver can be pro-
grammed to operate with the clock signals provided on either the TK or RK pins. This allows the
SSC to support many slave-mode data transfers. The maximum clock speed allowed on the TK
and RK pins is the master clock divided by 2.
The transmitter clock can be generated by:
• an external clock received on the TK I/O pad
• the receiver clock
• the internal clock divider
Interrupt Control
NVIC
RXEN
TX Start
RF
RC0R
TXEN
RX Start
TF
TX Clock
RK Input
TK Input
RX clock
Selector
Selector
Start
Start
Receive Holding
Transmit Holding
Register
Register
Transmitter
Transmit Clock
Receive Shift Register
TX Start
Receive Clock
Transmit Shift Register
Controller
Controller
Receiver
RX Start
Holding Register
Holding Register
RX Clock
Receive Sync
TX clock
Transmit Sync
Clock Output
Frame Sync
Clock Output
Frame Sync
Controller
Controller
Controller
Controller
Data
Controller
Controller
Data
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
TD
RK
RF
RD
TK
TF
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