TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 122

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

3.8
16-Bit Timer/Event Counters (TMRB)
following operation modes:
counter consists of a 16-bit up counter, two 16-bit timer registers (One of them with a
double-buffer structure), two 16-bit capture registers, two comparators, a capture input
controller, a timer flip-flop and a control circuit.
The TMP92CM22 contains 2 channels 16-bit timer/event counter (TMRB) which have the
Can be used following operation modes by capture function:
Figure 3.8.1 to Figure 3.8.2 show block diagram of TMRB0 and TMRB1. Each timer/event
Each timer/event counter is controlled by 11-byte control register (SFR).
This chapter consists of the following items:
3.8.1 Block diagram
3.8.2 Operation
3.8.3 SFRs
3.8.4 Operation in Each Mode
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Spec
External pin
(Address)
(1) 16-bit interval timer mode
(2) 16-bit event/counter mode
(3) 16-bit programmable pulse generation (PPG) output mode
(4) Capture function examples
SFR
16-bit interval timer mode
16-bit event counter mode
16-bit programmable square wave pulse generation output mode (PPG: Variable duty
cycle with variable period)
Frequency measurement mode
Pulse width measurement mode
Time differential measurement mode
External clock/
Caputre triggr input pin
Timer flip-flop output pin
Timre run register
Timre flip-flop control register
Timer register
Capture register
Timrer mode register
Table 3.8.1 Pins and SFR of TMRB
92CM22-120
Channel
TB0OUT0
(Share with PC6)
TB0RUN (1180H)
TB0MOD (1182H)
TB0FFCR (1183H)
TB0RG0L (1188H)
TB0RG0H (1189H)
TB0RG1L (118AH)
TB0RG1H (118BH)
TB0CP0L (118CH)
TB0CP0H (118DH)
TB0CP1L (118EH)
TB0CP1H (118FH)
TMRB0
None
TB1IN0 (Share with PD0)
TB1IN1 (Share with PD1)
TB1OUT0 (Share with PD2)
TB1OUT1 (Share with PD3)
TB1RUN (1190H)
TB1MOD (1192H)
TB1FFCR (1193H)
TB1RG0L (1198H)
TB1RG0H (1199H)
TB1RG1L (119AH)
TB1RG1H (119BH)
TB1CP0L (119CH)
TB1CP0H (119DH)
TB1CP1L (119EH)
TB1CP1H (119FH)
TMRB1
TMP92CM22
2007-02-16