TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 99

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

3.6.6
Caution
of the chip select signal, it is possible that an unintended read cycle occurs due to a delay
in the read signal. Such an unintended read cycle may cause a trouble as in the case of (a)
in Figure 3.6.3
same value of the toggle bit, and cannot read the toggle bit correctly. To avoid this
phenomenon, the data polling control recommended.
If the parasitic capacitance of the read signal (Output enable signal) is greater than that
Example: When using an externally connected flash EEPROM which users JEDEC
When the toggle bit reverse with this unexpected read cycle, TMP92CM22 always reads
standard commands, note that the toggle bit may not be read out correctly. If
the read signal in the cycle immediately preceding the access to the flash
EEPROM does not go “high” in time, as shown in Figure 3.6.4 an unintended
read cycle like the one shown in (b) may occur.
Flash EEPROM
Figure 3.6.4 Flash EEPROM Toggle Bit Read Cycle
Figure 3.6.3 Read Signal Delay Read Cycle
chip select
chip select
chip select
Memory 1
Memory 2
Toggle bit
CLKOUT
(20 MHz)
CLKOUT
(20 MHz)
Address
Address
Read
RD
Memory
access
92CM22-97
(b)
Toggle bit
RD cycle 1
(a)
TMP92CM22
2007-02-16