TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 50

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

(7) Notes
Note: The following instructions or pin input state changes are equivalent to instructions
independently. Therefore if, immediately before an interrupt is generated, the CPU
fetches an instruction which clears the corresponding interrupt request flag (Note), the
CPU may execute this instruction in between accepting the interrupt and reading the
interrupt vector. In this case, the CPU will read the default vector 0004H and jump to
interrupt vector address FFFF04H.
placed after a DI instruction. And in the case of setting an interrupt enable again by
EI instruction after the execution of clearing instruction, execute EI instruction after
clearing and more than 3-instructions (e.g., “NOP”× 3 times).
instruction, interrupt will be enable before request flag is cleared. Thus, when be
changed interrupt request level to “0”, change it after cleared corresponding interrupt
request by INTCLR instruction.
execution, disable an interrupt by DI instruction before execution of POPSR
instruction.
special attention.
INT0 to INT3 level mode
The instruction execution unit and the bus interface unit in this CPU operate
To avoid this, an instruction which clears an interrupt request flag should always be
If placed EI instruction without waiting NOP instruction after execution of clearing
In the case of changing the value of the interrupt mask register <IFF2:0> by
In addition, please note that the following two circuits are exceptional and demand
that clear the interrupt request flag.
INT0 to INT 3: Instructions which switch to level mode after an interrupt request has
INTRX:
INTRX
been generated in edge mode.
The pin input change from high to low after interrupt request has
been generated in level mode. (“H” → “L”, “L” →“H”)
Instruction which read the receive buffer.
If the CPU enters the interrupt response sequence as a result of INT x (x = 0, 1, 2,
or 3) going from 0 to 1, INTx must then be held at 1 until the interrupt response
sequence has been completed. If INTx is set to Level mode so as to release a
Halt state, INTx must be held at 1 from the time INTx changes from 0 to 1 until the
Halt state is released. (Hence, it is necessary to ensure that input noise is not
interpreted as a 0, causing INTx to revert to 0 before the Halt state has been
released.)
which were set in level mode will not be cleared. Interrupt request flags must be
cleared using the following sequence.
When the mode changes from level mode to edge mode, interrupt request flags
In level mode INT0 to INT3 are not an edge-triggered interrupt. Hence, in level
mode the interrupt request flip-flop for INT0 to INT3 does not function. The
peripheral interrupt request passes through the S input of the flip-flop and
becomes the Q output. If the interrupt input mode is changed from edge mode
to level mode, the interrupt request flag is cleared automatically.
The interrupt request flip-flop can only be cleared by a reset or by reading the
serial channel receive buffer. It cannot be cleared by writing INTCLR register.
92CM22-48
DI
LD (IIMC), 00H
LD (INTCLR), 0AH ; Clears interrupt request flag.
NOP
NOP
NOP
EI
; Changes from level to edge.
; Wait EI execution.
TMP92CM22
2007-02-16