TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 37

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

destination addresses are 32 bits wide, this type of register can only output 24-bit
addresses. Accordingly, micro DMA can only access 16 Mbytes (the upper eight bits of a
32-bit address are not valid).
(one-word) transfer and four-byte transfer. After a transfer in any mode, the transfer
source and transfer destination addresses will either be incremented or decremented,
or will remain unchanged. This simplifies the transfer of data from memory to memory,
from I/O to memory, from memory to I/O, and from I/O to I/O. For details of the various
transfer modes, see section 3.4.2 (1), detailed description of the transfer mode register.
operations can be performed per interrupt source (provided that the transfer counter
for the source is initially set to 0000H).
interrupts shown in the micro DMA start vectors in Table 3.4.1 and a micro DMA soft
start.
destination address INC mode (micro DMA transfers are the same in every mode
except counter mode). (The conditions for this cycle are as follows: Both source and
destination memory are internal RAM and multiples by 4 numbered source and
destination addresses.)
Although the control registers used for setting the transfer source and transfer
Three micro DMA transfer modes are supported: one-byte transfers, two-byte
Since a transfer counter is a 16-bit counter, up to 65536 micro DMA processing
Micro DMA processing can be initiated by any one of 34 different interrupts – the 33
Figure 3.4.2 shows a 2-byte transfer carried out using a micro DMA cycle in transfer
A0 to A23
States 1 to 2:
CLK
State 3:
State 4:
State 5:
Figure 3.4.2 Timing for Micro DMA Cycle
1 state
a.
Instruction fetches cycle (Gets next address code).
If the instruction queue buffer is FULL , this cycle becomes a dummy
cycle.
Micro DMA read cycle.
Micro DMA writes cycle.
(The same as in state 1, 2.)
b.
92CM22-35
src
c.
d.
dst
e.
TMP92CM22
2007-02-16