TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 153
TMP92xy22FG
Manufacturer Part Number
TMP92xy22FG
Description
Manufacturer
Toshiba
Datasheet
1.TMP92XY22FG.pdf
(260 pages)
Specifications of TMP92xy22FG
Package
LQFP100
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
32
Architecture
32-bit CISC
Usb/spi Channels
-
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
-
Adc 10-bit Channel
8
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
2
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
-
Number Of I/o Ports
50
Power Supply Voltage(v)
3.0 to 3.6
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Timing of writing data to
transmission buffer
Note 1: If the
Note 2: Transmission starts on the first falling edge of the TXDCLK clock after the
Handshake function
SIOCLK
TXDCLK
TXD
CTS
errors can be avoided. The handshake function is enabled or disabled by the
SC0MOD0<CTSE> setting.
transmission, data transmission is halted until the
However, the INTTX0 interrupt is generated, and it requests the next send from data
to the CPU. The next data is written in the transmission buffer and data transmission
is halted.
setting any port assigned to be the
request send data halt after data receive is completed by software in the receive
interrupt routine.
current transmission.
Use of
When the
Though there is no
a
Send is suspended
from a to b.
CTS
Transmission side
TMP92CM22
CTS0
signal goes high during transmission, will be stop next transmission data after completion of the
Figure 3.9.6
CTS0
13
pin allows data to be sent in units of one data format; thus, overrun
TXD
Figure 3.9.5 Handshake Function
CTS
pin condition is high level, after completed the current data
14
b
CTS
RTS
15
92CM22-151
(Clear to send) Signal Timing
pin, a handshake function can be easily configured by
16
RTS
1
Start bit
function. The
2
RTS
RXD
3
Receiving side
TMP92CM22
(Any port)
RTS
14
CTS0
CTS
should be output “High” to
15
pin state is low again.
signal has fallen.
16
1
TMP92CM22
2007-02-16
2
Bit0
3
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