TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 86

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

(4) Wait control
BnWW2
BnWR2
MHz).
the read cycle and the write cycle. BnWW is set with the same method as BnWR.
BnREC Bit (BnCSH register)
(i) Waits number fixed mode
(ii)
The external bus cycle completes a wait of two states at least (100 ns at f
Setting the <BnWW2:0> and <BnWR2:0> of BnCSL specifies the number of waits in
0
0
1
1
1
0
from 2 states (0 waits) to 6 states (4 waits).
pin state and inserts a wait if the pin is active. The bus cycle is minimum 2 states.
The bus cycle is completed when the wait signal is non-active (“High” level) at 2
states. The bus cycle extends if the wait signal is active at 2 states and more.
(tDF)), each other’s data-bus-output-recovery-time is trouble. However, by setting
BnREC of control register (BnCSH), can to insert dummy cycle of 1-state just
before first bus cycle of starting access another block address.
WAIT
0
1
The bus cycle is completed with the set states. The number of states is selected
This mode samples the
If a lot of connected pertain ROM and etc. (Much data-output-floating-time
pin input mode
BnWW1
BnWR1
No dummy cycle is inserted (Default).
Dummy cycle is inserted.
Others
0
1
0
1
1
1
BnWW/BnWR Bit (BnCSL Register)
BnWW0
BnWR0
92CM22-84
1
0
1
0
1
1
WAIT
input pins. It continuously samples the
2 states (0 waits) access fixed mode
3 states (1 wait) access fixed mode (Default)
4 states (2 waits) access fixed mode
5 states (3 waits) access fixed mode
6 states (4 waits) access fixed mode
(Reserved)
WAIT
pin input mode
Function
TMP92CM22
2007-02-16
SYS
WAIT
= 20