TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 72

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

3.5.10
Note: Can not read the output latch data when output mode.
Port D (PD0 to PD3)
output. Resetting sets port D to input port.
input pin (INT4 and INT5)/output pin (TB0IN, TB1OUT, TB3OUT, and TB1OUT1).
(1) PD0 (INT4, TB1IN0), PD1 (INT5, TB1IN1)
Port D is 4-bit general-purpose I/O port. Each bit can be set individually for input or
In addition to functioning as a general-purpose I/O port, port D can also function as an
These settings operate by programming “1” to the corresponding bit of PDCR and PDFC.
Resetting resets the PDCR and PDFC to “0”, and sets all bits to input port.
interrupt input pins INT4, INT5, timer channel input pins TB1IN0 and TB1IN1.
In addition to function as I/O port, port PD0 and PD1 can also function as external
Reset
INT4, TB1IN0
INT5, TB1IN1
Direction control
Function control
(on bit basis)
(on bit basis)
Output latch
PDCR write
PDFC write
PD read
PD write
S
Figure 3.5.22 Port D (PD0 and PD1)
92CM22-70
Selector
S
B
A
PD0 (INT4, TB1IN0)
PD1 (INT5, TB1IN1)
TMP92CM22
2007-02-16