TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 96

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

(1) Block address area specification register
MnS<23:16>
M0V<20:8>
M1V<21:8>
MnV<22:15>
Bit symbol
Read/Write
After reset
Bit symbol
Read/Write
After reset
Bit symbol
Read/Write
After reset
Bit symbol
Read/Write
After reset
address register (MSARn) and the memory address mask register (MAMRn). The
memory start address register sets all start address similarly regardless of the block
address areas. The bit to be set by the memory address mask register is depended on
the block address area.
The bit of M0V14 to M0V9 is corresponding to address A14 to A9 by 1 bit. If “0” is set, the comparison between
the value of the address bus and the start address is enabled. If “1” is set, the comparison is masked.
The bits of M1V15 to M1V9 are corresponding to address A15 to A9 by 1 bit. If “0” is set, the comparison between
the value of the address bus and the start address is enabled. If “1” is set, the comparison is masked.
If “0” is set, the comparison between the value of the address bus and the start address is enabled. If “1” is set,
the comparison is masked.
B3CSH<B3E> are reset to “0”. This disables the CS0, CS1, and CS3 areas. However, B2CSH<B2M> is reset to
“0” and B2CSH<B2E> to “1”, and CS2 is enabled 000000H to FFFFFFH. Also the bus width and the number of
waits specified in BEXCSH/L are used for accessing address except the specified CS0 to CS3 area.
A start address and range in the block address are specified by the memory start
Sets a start address.
Sets the start address of the block address areas. The bit is corresponding to the address A23 to A16.
Enables or masks comparison of the addresses. M0V20 to M0V8 are corresponding to addresses A20 to A8.
Enables or masks comparison of the addresses. M1V21 to M1V8 are corresponding to addresses A21 to A8.
Enables or masks comparison of the addresses. MnV22 to MnV15 are corresponding to addresses A22 to A15.
After a reset, MASR0 to MASR3 and MAMR0 to MAMR3 are set to “FFH”. B0CSH<B0E>, B1CSH<B1E>, and
M0V20
M1V21
MnS23
MnV22
7
7
1
1
1
1
7
7
MnS22
M0V19
M1V20
MnV21
1
6
6
1
1
6
1
6
MAMRn (n = 2 to 3)
MSARn (n = 0 to 3)
92CM22-94
MnS21
M0V18
M1V19
MnV20
MAMR0
MAMR1
1
5
5
5
1
1
1
5
MnS20
M0V17
M1V18
MnV19
1
4
4
4
1
1
1
4
R/W
R/W
R/W
R/W
MnS19
M0V16
M1V17
MnV18
1
3
3
3
1
1
1
3
MnS18
M0V15
M1V16
MnV17
1
2
2
2
1
1
1
2
MnS17
M0V14-9
M1V15-9
MnV16
1
1
1
1
1
1
1
1
TMP92CM22
2007-02-16
MnS16
1
MnV15
0
M0V8
M1V8
0
0
1
1
1
0