TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 146

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

SCLK1 input
(Shared
SCLK1 output
(Shared
RXD1
(Shared
with PF5)
with PF5)
with PF4)
φT0
f
io
SC1MOD0
<RXE>
φT0
φT2
φT8
φT32
RXDCLK
Serial clock generation circuit
I/O interface mode
RB8
BR1CR<BR1CK1:0>
2
Receive buffer 1 (Shift register)
φT2
(UART only ÷ 16)
Receive control
4 8 16 32
Receive buffer
Prescaler
Receive buffer 2 (SC1BUF)
Baud rate generater
φT8
<BR1S3:0>
BR1CR
φT32
<BR1ADDE>
64
BR1CR
SC1MOD0
Figure 3.9.3 Block Diagram of SIO1
<WU>
<BR1K3:0>
BR1ADD
<OERR> <PERR> <FERR>
92CM22-144
÷ 2
<PE>
interrupt control
Serial channel
Internal data bus
Parity control
(from TMRA0)
Error flag
SC1CR
SC1CR
SC1MOD0
<SC1:0>
SC1CR
<IOC>
<EVEN>
TA0TRG
I/O interface mode
UART
mode
SC1MOD0
<SM1:0>
TXDCLK
TB8
(UART only ÷ 16)
Transmission
Transmission
Transmission buffer
SIOCLK
counter
control
(SC1BUF)
SC1MOD0
<CTSE>
TMP92CM22
2007-02-16
(Shared
(Shared
Interrupt request
with PF5)
INTRX1
INTTX1
with PF3)
CTS1
TXD1