TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 176

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

Read-
modify-write
instruction is
prohibited.
SBI0CR1
(1240H)
3.10.4
Bit symbol
Read/Write
After reset
Function
Note 1: Set the <BC2:0> to “000” before switching to a clocked-synchronous 8-bit SIO mode.
Note 2: For the frequency of the SCL line clock, see section 3.10.5 (3) “Serial clock”.
Note 3: Initial data of SCK0 is “0”, SWRMON is “1”.
Note 4: This I
I
the serial bus interface (SBI) in the I
2
C Bus Mode Control Register
The following registers are used to control and monitor the operation status when using
itself allows the setting of a baud rate over 100 kbps, the compliance with the I
guaranteed in that case.
Select number of transferred bits
(Note 1)
2
C bus circuit does not support Fast mode, it supports standard mode only. Although the I
BC2
7
0
Figure 3.10.3 Register for I
Serial Bus Interface Control Register 1
BC1
W
6
0
BC0
92CM22-174
5
0
2
C bus mode.
Acknowledge
mode
specification
0: Not
1: Generate
Internal serial clock selection <SCK2:0> at write
000
001
010
011
100
101
110
111
Software reset state monitor <SWRMON> at read
Acknowledge mode selection
Select number of bits transferred
generate
<BC2:0>
ACK
R/W
0
1
0
1
4
0
000
001
010
011
100
101
110
111
(Reserved)
2
During software reset
Initial data
Not generate clock pulse for acknowledge signal
Generate clock for acknowledge signal
C Bus Mode
n = 10
n = 11
n = 5
n = 6
n = 7
n = 8
n = 9
Number of
pulses
clock
3
8
1
2
3
4
5
6
7
− kHz (Note4)
− kHz (Note4)
− kHz (Note4)
<ACK> = 0
(Reserved)
75.8 kHz
38.5 kHz
19.4 kHz
9.73 kHz
Internal serial clock selection and
software reset monitor
(Note 2)
Data length
SCK2
2
0
8
1
2
3
4
5
6
7
System clock: f
W
f
SCL pin)
Frequency =
SYS
2
C specification is not
Number of
SCK1
= 20 MHz (output to
pulses
clock
1
0
9
2
3
4
5
6
7
8
<ACK> = 1
TMP92CM22
2
C bus circuit
2007-02-16
2
SYS
f
0/1 (Note 3)
n
SYS
SWRMON
Data length
+ 8
SCK0/
R/W
0
8
1
2
3
4
5
6
7
[Hz]