TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 181

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

Internal SCL output
(Master A)
Internal SCL output
(Master B)
SCL line
(4) Slave address and address recognition mode specification
(5) Master/slave selection
<ALS> to the I2C0AR. Clear the <ALS> to “0” for the address recognition mode.
Clear the SBI0CR2<MST> to “0” for operation as a slave device. The <MST> is cleared
to “0” by the hardware after a stop condition on the bus is detected or arbitration is lost.
2.
When the TMP92CM22 is used as a slave device, set the slave address <SA6:0> and
Set the SBI0CR2<MST> to “1” for operating the TMP92CM22 as a master device.
Clock synchronization
down a clock line to low level, in the first place, invalidate a clock pulse of another
master device which generates a high-level clock pulse. The master device with a
high-level clock pulse needs to detect the situation and implement the following
procedure.
even when more than one master exists on the bus.
simultaneously exist on a bus.
SCL line of the bus becomes the low level. After detecting this situation, master B
resets a counter of high-level width of an own clock pulse and sets the internal
SCL output to the low level.
and sets the internal SCL output to the high level. Since master B holds the SCL
line of the bus at the low level, master A waits for counting high-level width of an
own clock pulse. After master B finishes counting low-level width of an own clock
pulse at point “c” and master A detects the SCL line of the bus at the high level,
and starts counting high level of an own clock pulse. The clock pulse on the bus is
determined by the master device with the shortest high-level width and the
master device with the longest low-level width from among those master devices
connected to the bus.
In the I
The TMP92CM22 has a clock synchronization function for normal data transfer
The example explains the clock synchronization procedures when two masters
As master A pulls down the internal SCL output to the low level at point “a”, the
Master A finishes counting low-level width of an own clock pulse at point “b”
2
C bus mode, in order to wired-AND a bus, a master device which pulls
Figure 3.10.8 Clock Synchronization
a
Reset a counter of
high-level width of
a clock pulse
92CM22-179
Wait counting high-level
width of a clock pulse
b
c
Start couting high-level width of a clock pulse
TMP92CM22
2007-02-16