TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 126

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

The timer registers are write-only registers and thus cannot be read.
(3) Timer registers (TB0RG0H/L and TB0RG1H/L)
counter UC10 matches the value set in this timer register, the comparator match
detect signal will go active.
is always needed. For example, either using 2-byte data transfer instruction or using
1-byte data transfer instruction twice for lower 8 bits and upper 8 bits in order.
register buffer 10. The value set in TB0RUN<TB0RDE> determines whether the
double-buffer structure is enabled or disabled: It is disabled when <TB0RDE> = 0, and
enabled when <TB0RDE> = 1.
timer register when the values in the up counter (UC10) and the timer register
TB0RG1H/L match.
used after a reset, data should be written to it beforehand.
double buffer, write data to the timer register, set <TB0RDE> to 1, then write data to
the register buffer as shown below.
(001188H and 001189H) allocated to them. If <TB0RDE> = 0, the value is written to
both the timer register and the register buffer. If <TB0RDE> = 1, the value is written
to the register buffer only.
These two 16-bit registers are used to set the interval time. When the value in the up
Setting data for both upper and lower timer registers TB0RG0H/L and TB0RG1H/L
The TB0RG0H/L timer register has a double-buffer structure, which is paired with
When the double buffer is enabled, data is transferred from the register buffer to the
After a reset, TB0RG0H/L and TB0RG1H/L are undefined. If the 16-bit timer is to be
On a reset <TB0RDE> is initialized to 0, disabling the double buffer. To use the
TB0RG0H/L and the register buffer both have the same memory addresses
The addresses of the timer registers are as follows:
TMRB0
TMRB1
Upper 8 bits
Upper 8 bits
(TB0RG0H)
(TB1RG0H)
1189H
1199H
TB0RG0H/L
TB1RG0H/L
Lower 8 bits
Lower 8 bits
(TB0RG0L)
(TB1RG0L)
92CM22-124
1188H
1198H
Upper 8 bits
Upper 8 bits
(TB0RG1H)
(TB1RG1H)
118BH
119BH
TB0RG1H/L
TB1RG1H/L
Lower 8 bits
Lower 8 bits
(TB0RG1L)
(TB1RG1L)
118AH
119AH
TMP92CM22
2007-02-16