TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 191

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

SCL (bus)
SCL pin
SDA pin
<LRB>
<BB>
<PIN>
(5) Restart
change the data transfer direction. The following description explains how to restart
when this device is in the master mode.
release the bus. The SDA line remains the high level and the SCL pin is released. Since
a stop condition is not generated on the bus, other devices assume the bus to be in a
busy state. Check the SBI0SR<BB> until it becomes “0” to check that the SCL pin of
this device is released. Check the <LRB> until it becomes 1 to check that the SCL line
on a bus is not pulled down to the low level by other devices. After confirming that the
bus stays in a free state, generate a start condition with procedure described in 3.10.6
(2).
software from the time of restarting to confirm that the bus is free until the time to
generate the start condition.
Restart is used during data transfer between a master device and a slave device to
Clear the SBI0CR2<MST, TRX, BB> to “000” and set the SBI0CR2<PIN> to “1” to
In order to meet setup time when restarting, take at least 4.7 μs of waiting time by
9
“0” → <MST>
“0” → <TRX>
“0” → <BB>
“1” → <PIN>
Figure 3.10.19 Timing Diagram when Restarting
92CM22-189
“1” → <MST>
“1” → <TRX>
“1” → <BB>
“1” → <PIN>
4.7 μs (Min)
Start condition
TMP92CM22
2007-02-16