TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 24

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

3.3.6
*: Except clocked-synchronous 8-bit SIO mode for SBI.
CPU
I/O port
TMRA, TMRB
SIO, *SBI
AD converter
WDT
SYSCR2<HALTM1:0>
Standby Controller
(1) HALT modes
a.
HALT Mode
IDLE1, or STOP mode, depending on the contents of the SYSCR2<HALTM1:0>
register.
When the HALT instruction is executed, the operating mode switches to IDLE2,
The subsequent actions performed in each mode are as follows:
IDLE2: Only the CPU halts.
The internal I/O is available to select operation during IDLE2 mode by setting the
following register.
Table 3.3.1 shows the registers of setting operation during IDLE2 mode.
b.
c.
Table 3.3.1 SFR Seting Operation during IDLE2 Mode
The operation of each of the different HALT modes is described in Table 3.3.2.
Table 3.3.2 Each Block Operation in HALT Mode
TMRA01
TMRA23
TMRB0
TMRB1
SIO0
SIO1
AD converter
WDT
SBI
IDLE1: Only internal oscillator operates.
STOP: All internal circuit stop.
Internal I/O
instruction is executed.
* Selection enable operation
Keep the state when the HALT
block to programmable
92CM22-22
IDLE2
11
TA01RUN<I2TA01>
TA23RUN<I2TA23>
TB0RUN<I2TB0>
TB1RUN<I2TB1>
SC0MOD1<I2S0>
SC1MOD1<I2S1>
ADMOD1<I2AD>
WDMOD<I2WDT>
SBI0BR0<I2SBI0>
SFR
Stop
Refer Table 3.3.5, Table 3.3.6
IDLE1
10
Stop
STOP
01
TMP92CM22
2007-02-16