TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 131

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

Read-modify
-write
instruction is
prohibited
TB1MOD
(1192H)
Bit symbol
Read/Write
After reset
Function
TB1FF1 Inversion trigger
0: Trigger disable
1: Trigger enable
Invert when
UC12 is
loaded into
TB1CP1H/L
TB1CT1
7
0
R/W
Invert when
UC12
matches
with
TB1RG1H/L
TB1ET1
6
0
Figure 3.8.5 Register for TMRB
TMRB1 Mode Register
Software
capture
control
0: Software
1: Undefined
TB1CP0I
capture
92CM22-129
W
5
1
Capture timing
00: Disable
01: TB1N0 ↑ TB1IN1 ↑
10: TB1IN0 ↑ TB1IN0 ↓
11: TA1TRG ↑
TB1CPM1
Input clock
00 TB1IN0 pin input
01 φT1
10 φT4
11 φT16
00 Capture disable
01
10
11
0
1
0
1
Clear up counter (UC12)
Capture/interrupt timing
Software capture
4
0
INT4 is rising edge
INT4 is falling edge
INT4 is falling edge
TA1TRG ↓
INT4 is rising edge
Capture to TB1CP0H/L at rising edge of TB1IN0
Capture to TB1CP1H/L at rising edge of TB1IN1
Capture to TB1CP0H/L at rising edge of TB1IN0
Capture to TB1CP1H/L at falling edge of TB1IN1
Capture to TB1CP0H/L at rising edge of TA1OUT
Capture to TB1CP1H/L at falling edge of TA1OUT
Clear disable
Clear by matching with TB1RG1H/L
Capture value of up counter to TB1CP0H/L
Undefined
TB1CPM0
3
0
Capture control
Up counter
control
0: Clear
1: Clear
TB1CLE
disable
enable
R/W
2
0
00: TB1IN0 pin input
01: φT1
10: φT4
11: φT16
TMRB1 source clock
TB1CLK1
1
0
TMP92CM22
Generate INT4
by TB1IN0
rising
Generate INT4
by TB1IN0
falling
Generate INT4
by TB1IN0
rising
2007-02-16
INT4 control
TB1CLK0
0
0