TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 81

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

3.6.2
Control Register and Operation after Reset Release
release and necessary settings.
(1) Control register
(2) Operation after reset release
This section describes the registers to control the memory controller, the state after reset
following registers to control ROM page mode access.
just after reset release. Then, the external memory is accessed as follows.
The control registers of the memory controller are as follows.
In addition to setting of the above-mentioned registers, it is necessary to set the
The start data bus width is determined depending on state of AM1 and AM0 pins
•
•
•
•
data bus width is set to the value set to BnBUS bit of the control register.
automatically effective (B2CSH<B2E> is set to “1” by reset).
specify the bus width of the control register in the block address area 2.
address register (MSAR) and the memory address mask register (MAMR). Then
the control register (BnCS) is set.
AM1/AM0 pins are valid only just after reset release. In the other cases, the
By reset, only control register (B2CSH/B2CSL) of the block address area 2 is
The data bus width which is specified by AM1/AM0 pin is loaded to the bit to
The block address area 2 is set to address 000000H to FFFFFFH by reset.
After reset release, the block address areas are specified by the memory start
Set the enable bit (BnE) of the control register to “1” to enable the setting.
Control register: BnCSH/BnCSL (n = 0 to 3, EX)
Sets the basic functions of the memory controller, that is the connecting
memory type, the number of waits to be read and written.
Memory start address register: MSARn (n = 0 to 3)
Sets a start address in the selected block address areas.
Memory address mask register: MAMRn (n = 0 to 3)
Sets a block size in the selected address areas.
Page ROM control register: PMEMCR
Sets to executed ROM page mode accessing.
AM1
0
0
1
1
AM0
0
1
0
1
92CM22-79
Start with 16-bit data bus
Start with 8-bit data bus
Don’t use this setting
Don’t use this setting
Start Mode
TMP92CM22
2007-02-16