TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 25

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

(2) How to release the HALT mode
release sources are determined by the combination between the states of interrupt
mask register <IFF2:0> and the HALT modes. The details for release the halt status
are shown in Table 3.3.3.
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•
These halt states can be released by resetting or requesting an interrupt. The halt
Released by requesting an interrupt
Release by resetting
status. When the interrupt request level set before executing the HALT
instruction exceeds the value of interrupt mask register, the interrupt due to the
source is processed after release the HALT mode, and CPU status executing an
instruction that follows the HALT instruction. When the interrupt request level
set before executing the HALT instruction is less than the value of the interrupt
mask register, release the HALT mode is not executed. (In non-maskable
interrupts, interrupt processing is processed after release the HALT mode
regardless of the value of the mask register.) However only for INT0 to INT3
interrupts, even if the interrupt request level set before executing the HALT
instruction is less than the value of the interrupt mask register, release the HALT
mode is executed. In this case, interrupt processing, and CPU starts executing the
instruction next to the HALT instruction, but the interrupt request flag is held at
“1”.
time (Refer Table 3.3.4) to set the operation of the oscillator to be stable.
state before the “HALT” instruction is executed. However the other settings
contents are initialized. (Release due to interrupts keeps the state before the
“HALT” instruction is executed.)
The operating released from the HALT mode depends on the interrupt enabled
Release all halt status is executed by resetting.
When the STOP mode is released by RESET, it is necessary enough resetting
When release the HALT mode by resetting, the internal RAM data keeps the
92CM22-23
TMP92CM22
2007-02-16