TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 47

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

Symbol
INTCLR
Interrupt
Name
control
clear
(4) Interrupt request flag clear register
(5) Micro DMA start vector registers
vector, as given in Table 3.4.1, to the register INTCLR.
operation after execution of the DI instruction.
source with a micro DMA start vector that matches the vector set in this register is
assigned as the micro DMA start source.
end interrupt corresponding to the channel is sent to the interrupt controller, the micro
DMA start vector register is cleared, and the micro DMA start source for the channel is
cleared. Therefore, to continue micro DMA processing, set the micro DMA start vector
register again during the processing of the micro DMA transfer end interrupt.
channel, the channel with the lowest number has a higher priority. Accordingly, if the
same vector is set in the micro DMA start vector registers of two channels, the
interrupt generated in the channel with the lower number is executed until micro DMA
transfer is completed. If the micro DMA start vector for this channel is not set again,
the next micro DMA is started for the channel with the higher number (Micro DMA
chaining).
Address
The interrupt request flag is cleared by writing the appropriate micro DMA start
For example, to clear the interrupt flag INT0, perform the following register
INTCLR ← 0AH Clears interrupt request flag INT0
This register assigns micro DMA processing to which interrupt source. The interrupt
When the micro DMA transfer counter value reaches “0”, the micro DMA transfer
If the same vector is set in the micro DMA start vector registers of more than one
(Prohibit
RMW)
F8H
7
6
92CM22-45
CLRV5
5
0
CLRV4
4
0
CLRV3
Interrupt clear
3
0
W
CLRV2
2
0
CLRV1
1
0
TMP92CM22
2007-02-16
CLRV0
0
0