TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 127

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

The capture registers are read-only registers and thus cannot be written.
(4) Capture registers (TB0CP0H/L, TB0CP1H/L, TB1CP0H/L and TB1CP1H/L)
(5) Capture and external interrupt control
example, using 2-byte data transfer instruction or using 1-byte data transfer
instruction twice for lower 8 bits and upper 8 bits in order.
TB0CP0H/L, TB0CP1H/L and generating for external interrupt.
by TB0MOD<TB0CPM1:0>. (TMRB0 does not include the selection edge of external
interrupt.) External interrupt INT5 is fixed to rising edge.
Whenever 0 is programmed to TB0MOD<TB0CP0I>, the current value in the up
counter is loaded into capture register TB0CP0. It is necessary to keep the prescaler in
Run mode (e.g., TB0RUN<TB0PRUN> must be held at a value of 1).
These 16-bit registers are used to latch the values in the up counters UC10.
Data in the capture registers should be read both upper and lower all 16 bits. For
The addresses of the capture registers are as follows:
This circuit controls the timing to latch the value of up counter UC10 into
Interrupt timing of capture register and selection edge of external interrupt are set
The value in the up counter (UC10) can be loaded into a capture register by software.
TMRB0
TMRB1
Upper 8 bits
Upper 8 bits
(TB0CP0H)
(TB1CP0H)
118DH
119DH
TB0CP0H/L
TB1CP0H/L
92CM22-125
Lower 8 bits
Lower 8 bits
(TB0CP0L)
(TB1CP0L)
118CH
119CH
Upper 8 bits
Upper 8 bits
(TB0CP1H)
(TB1CP1H)
118FH
119FH
TB0CP1H/L
TB1CP1H/L
Lower 8 bits
Lower 8 bits
(TB0CP1L)
(TB1CP1L)
118EH
119EH
TMP92CM22
2007-02-16