TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 180

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TMP92xy22FG

Manufacturer Part Number
TMP92xy22FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP92xy22FG

Package
LQFP100
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
32
Architecture
32-bit CISC
Usb/spi Channels
-
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
-
Adc 10-bit Channel
8
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
2
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
-
Number Of I/o Ports
50
Power Supply Voltage(v)
3.0 to 3.6
3.10.5
Control in I
(1) Acknowledge mode specification
(2) Select number of transfer bits
(3) Serial clock
TMP92CM22 generates an additional clock pulse for an acknowledge signal when
operating in master mode. In the transmitter mode during the clock pulse cycle, the
SDA pin is released in order to receive the acknowledge signal from the receiver. In the
receiver mode during the clock pulse cycle, the SDA pin is set to the low in order to
generate the acknowledge signal.
does not generate a clock pulse for the acknowledge signal when operating in the
master mode.
receiving data.
direction bit are transferred in 8 bits. Other than these, the <BC2:0> retains a
specified value.
on the SCL pin in master mode. Set the baud rates, which have been calculated
according to the formula below, to meet the specifications of the I
smallest pulse width of t
Note: f
1.
Set the SBI0CR1<ACK> to 1 for operation in the acknowledge mode. The
Clear the <ACK> to 0 for operation in the non-acknowledge mode, the TMP92CM22
The SBI0CR1<BC2:0> is used to select a number of bits for next transmission/
Since the <BC2:0> is cleared to 000 as a start condition, a slave address and
The SBI0CR1<SCK2:0> is used to select a maximum transfer frequency outputted
Clock source
SBI
2
C Bus Mode
shows f
t
t
fscl = 1/(t
LOW
HIGH
=
= 2
t
= 2
HIGH
2
SYS
f
n
SBI
n − 1
LOW
+ 8
n − 1
.
/f
/f
SBI
SBI
+ t
Figure 3.10.7 Clock Source
HIGH
+ 8/f
t
LOW
LOW
)
SBI
92CM22-178
.
SBI0CR1<SCK2:0>
1/fscl
000
001
010
011
100
101
110
10
11
n
5
6
7
8
9
2
C bus, such as the
TMP92CM22
2007-02-16

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