TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 155

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

Note1: In 9 Bits mode and 8 Bits + Parity mode, interrupts coincide with the ninth bit pulse. Thus, when servicing the
Note2: The higher the transfer rate, the later than the middle receive interrupts and errors occur.
(12) Timing generation
2.
3.
1.
Receiving
Transmission
2.
Interrupt generation
timing
Framing error
generation timing
Parity error
generation timing
Overrun error
generation timing
Interrupt generation
timing
Transmission
interrupt
timing
Receiving
interrupt
timing
interrupt, it is necessary to wait for a 1-bit period (to allow the stop bit to be transferred) to allow checking for
a framing error.
Parity error <PERR>
The parity generated for the data shifted into receiving buffer 2 (SC0BUF) is
compared with the parity bit received via the RXD pin. If they are not equal, a
parity error is generated.
Framing error <FERR>
the majority of the samples are 0, a framing error is generated.
In UART mode
In I/O interface mode
The stop bit for the received data is sampled three times around the center. If
Mode
Mode
SCLK output mode
SCLK input mode
SCLK output mode
SCLK input mode
Just before stop bit is
transmitted
Center of last bit
(Bit8)
Center of stop bit
Center of last bit
(Bit8)
9 Bits
9 Bits
−
92CM22-153
Immediately after last bit data.
(See Figure 3.9.19.)
Immediately after rise of last SCLK signal rising mode, or
immediately after fall in falling mode. (See Figure 3.9.20.)
Timing used to transfer received to data receive buffer 2 (SC0BUF)
(e.g., immediately after last SCLK). (See Figure 3.9.21.)
Timing used to transfer received data to receive buffer 2 (SC0BUF)
(e.g., immediately after last SCLK). (See Figure 3.9.22.)
Center of last bit
(Parity bit)
Center of stop bit
Center of last bit
(Parity bit)
Center of last bit
(Parity bit)
8 Bits + Parity
8 Bits + Parity
←
8 Bits, 7 Bits + Parity, 7 Bits
8 Bits, 7 Bits + Parity, 7 Bits
Center of stop bit
Center of stop bit
Center of stop bit
Center of stop bit
←
TMP92CM22
2007-02-16