R1610C RDC Semiconductor, R1610C Datasheet - Page 10

• Manufacturer Part Number: R1610C
• Description: High Performance 16 Bits MCU Integrated One 10/100M Mac Controller - 3.3V Operating Voltage/2.5V Core Voltage
• Manufacturer: RDC Semiconductor

R
I = Input;
O = Output;
PU = Pull up 75KΩ;
PD = Pull down 75KΩ;
PU* = Pull up 75KΩ when the PIOn pin is used;
PD* = Pull down 75KΩ when the PIOn pin is used;
● CPU Core
R
Bus Interface
3.2 Functional Description
10
PIN No.
PIN No.
120
128
127
100
122
D
37
38
D
C
C
®
®
WR_n/BWSEL
R
R
I
I
S
S
CLKOUTA
C
C
Symbol
Symbol
D
D
RST_n
ARDY
S
RD_n
S
P
P
X1
X2
C
C
o
o
m
m
m
m
u
u
n
n
i
i
c
c
a
a
t
t
i
i
o
o
n
n
O/PU
Type
Type
I/PU
I/PU
O
O
O
I
Reset input with schmitt trigger. When RST_n is asserted, the
CPU immediately terminates all operations, clears the internal
registers & logic, and changes the address to the reset address
FFFF0h.
25MHz frequency input, within 100 ppm tolerance, to the
amplifier (oscillator).
Frequency output from the inverting amplifier (oscillator).
The CLKOUTA output frequency is the same as the X1 input
frequency.
When high, the CLKOUTA is from Multiple-PLL. When low, the
CLKOUTA is from X1.
Read Strobe. One active low signal indicates that the
microcontroller is performing a memory or I/O read cycle. The
RD_n floats during a bus hold or reset.
Write strobe. This pin indicates that the data on the bus is to be
written into a memory or an I/O device. WR_n is active during
T2, T3, and Tw of any write cycle, floating during a bus hold or
reset.
BWSEL is used to decide the boot ROM bus width when RST_n
goes from low to high.
If BWSEL is with an external pull-low resistor (4.7k ohm), the
boot ROM bus width is 8 bits. Otherwise the boot ROM width is
16 bits.
Asynchronous ready. This pin indicates to the microcontroller
that the addressed memory space or I/O device will complete a
data transfer. The ARDY pin accepts a rising edge of input that
is asynchronous to SD_CLK and is active high. However, the
falling edge of ARDY must be synchronized to SD_CLK. Tie
ARDY high, so the microcontroller is always asserted in the
ready condition. To guarantee the wait states inserted, ARDY
must be pulled low before to phase 2 of T2 or phase 1 of T3.
Please note that the ARDY signal is internally pulled high.
Description
Fast Ethernet RISC Processor
Description
R1610C
October 27, 2003
Final Version 1.5
Data Sheet