R1610C RDC Semiconductor, R1610C Datasheet - Page 129
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R1610C
Manufacturer Part Number
R1610C
Description
High Performance 16 Bits MCU Integrated One 10/100M Mac Controller - 3.3V Operating Voltage/2.5V Core Voltage
Manufacturer
RDC Semiconductor
Datasheet
1.R1610C.pdf
(145 pages)
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R
22.
Data Sheet
Final Version 1.5
October 27, 2003
R
No.
22.1
Parameter
22.2
10
11
12
13
14
15
16
17
1
2
6
7
9
Symbol
t
t
t
t
t
CHCSV
CHCSX
t
t
t
t
t
t
t
CLCSV
t
AVCH
AVWL
CHLH
AVRL
AZRL
CHLL
CLAX
CLAZ
CLDV
AVLL
Parameter
D
AC Electrical Characteristics
D
Symbol
t
t
t
CXCSX
t
t
t
t
t
t
t
CLCSV
t
t
t
DVCL
CLDX
CLDV
CHLH
AVCH
CLAX
CHLL
CLAZ
LHLL
AVLL
LLAX
C
Alphabetical Key to Switching Parameter Symbols
Numerical Key to Switching Parameter Symbols
C
No.
14 SAD Address Valid to Clock High
12 SAD Address Valid to ALE Low
66 SAD Address Valid to RD_n Low
65 SAD Address Valid to WR_n Low
24 SAD Address Float to RD_n Active
67
18 PCS_n Inactive Delay
11 ALE Inactive Delay
15 SAD Address Float Delay
16 PCS Active Delay
9 ALE Active Delay
6 Address Hold
7 Data Valid Delay
®
®
SD_CLK High to SDRAM
Interface/UCS_n Valid
Data in Setup
Data in Hold
Address Hold
Data Valid Delay
ALE Active Delay
ALE Width
ALE Inactive Delay
SAD Address Valid to ALE Low
SAD Address Hold from ALE Inactive
SAD Address Valid to Clock High
SAD Address Float Delay
PCS Active Delay
PCS_n Hold from Command Inactive
R
R
I
I
S
S
C
C
D
D
S
S
P
P
C
C
o
o
m
m
m
m
u
u
Description
n
n
Description
i
i
c
c
a
a
t
t
i
i
o
o
n
n
No.
18
24
25
26
27
28
29
32
57
59
65
66
67
Parameter
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
WLWH
t
RESIN
RHDX
CLDX
CLRH
DVCL
DXDL
RHAV
RHLH
RLRH
CLRL
LHLL
LLAX
Parameter
Symbol
t
t
t
t
CHCSX
t
t
t
t
t
t
CHCSV
t
t
t
WLWH
RESIN
RHDX
AVWL
RLRH
CLRH
RHLH
RHAV
AZRL
CLRL
AVRL
No.
27
25
17
10
13
57
29
59
28
26
32
2
1
PCS_n Inactive Delay
SAD Address Float to RD_n Active
RD_n Active Delay
RD_n Pulse Width
RD_n Inactive Delay
RD_n Inactive to ALE High
RD_n Inactive to SAD Address Active
WR_n Pulse Width
RST_n Setup Time
RD_n High to Data Hold on SAD Bus
SAD Address Valid to WR_n Low
SAD Address Valid to RD_n Low
SD_CLK High to SDRAM Interface/UCS_n
Valid
Data in Hold
RD_n Inactive Delay
RD_n Active Delay
PCS_n Hold from Command Inactive
Data in Setup
ALE Width
SAD Address Hold from ALE Inactive
RST_n Setup Time
RD_n Inactive to SAD Address Active
RD_n High to Data Hold on SAD Bus
RD_n Inactive to ALE High
RD_n Pulse Width
WR_n Pulse Width
Fast Ethernet RISC Processor
Description
Description
R1610C
129
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