R1610C RDC Semiconductor, R1610C Datasheet - Page 58

• Manufacturer Part Number: R1610C
• Description: High Performance 16 Bits MCU Integrated One 10/100M Mac Controller - 3.3V Operating Voltage/2.5V Core Voltage
• Manufacturer: RDC Semiconductor

R
R
DM/IO_n DDEC
15-0 DSA[15:0]
58
Register Offset:
Register Name:
Reset Value
Register Offset:
Register Name:
Reset Value
15
Bit
15
Bit
15
14
13
12
10
11
D
D
14
14
DM/IO_n
SM/IO_n
C
DDEC
SDEC
Name
Name
C
DINC
SINC
DINC DM/IO_n SDEC
13
13
®
®
:
:
R
R
I
I
S
S
Attribute
Attribute
C
C
C0h (DMA0)
DMA0 Source Address Low Register
──
DAh (DMA1)
DMA1 Control Register
0000h
D
D
12
12
S
S
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P
P
C
C
o
o
m
m
m
m
u
u
11
11
n
n
i
i
c
c
a
a
t
t
Low DMA 0 Source Address.
These bits are mapped to A[15:0] during a DMA transfer.
The value of DSA [19:0] will be incremented or decremented by 2 or 1 after each
DMA transfer.
Destination Address Space Select.
Set 1: The destination address is in memory space.
Set 0: The destination address is in I/O space.
Destination Decrement.
Set 1: The destination address is automatically decremented after each transfer.
Set 0: Disable the decrement function.
Destination Increment.
Set 1: The destination address is automatically incremented after each transfer.
Set 0: Disable the increment function.
Source Address Space Select.
Set 1: The Source address is in memory space.
Set 0: The Source address is in I/O space.
Source Decrement.
Set 1: The Source address is automatically decremented after each transfer. The
Set 0: Disable the decrement function.
Source Increment.
Set 1: The Source address is automatically incremented after each transfer. The
i
i
o
o
n
n
SINC
10
10
The B_n/W (bit 0) bit determines the decrement value which is by 1 or 2
when both DDEC and DINC bits are set to 1 or 0. The address remains
constant.
The B_n/W (bit 0) bit determines the incremented value is by 1 or 2.
B_n/W (bit 0) bit determines the decremented value is by 1 or 2 when both
SDEC and SINC bits are set to 1 or 0. The address remains constant.
TC
9
9
INT
DSA [15:0]
8
8
SYN1
7
7
SYN0
6
6
Description
Description
5
5
P
TDRQ
4
4
Fast Ethernet RISC Processor
EXT
3
3
CHG
2
2
ST
1
1
R1610C
B_n/W
October 27, 2003
0
0
Final Version 1.5
Data Sheet