R1610C RDC Semiconductor, R1610C Datasheet - Page 70

• Manufacturer Part Number: R1610C
• Description: High Performance 16 Bits MCU Integrated One 10/100M Mac Controller - 3.3V Operating Voltage/2.5V Core Voltage
• Manufacturer: RDC Semiconductor

R
after reset and the timeout count with a maximum count value. The keyed sequence (3333h, CCCCh) must be
written to the register (E6h) first, then the new configuration to the Watchdog Timer Control Register. It is a single
write, so every writing to the Watchdog Timer Control Register will follow this rule.
timer duration, the watchdog timeout happens. The keyed sequence (AAAAh, 5555h) must be written to the
register (E6h) to reset the internal count and prevent the watchdog timeout. The internal count should be reset
before the Watchdog Timer timeout period is modified to ensure that an immediate timeout will not occur.
R
15.2
ENA
70
Register Offset:
Register Name:
Reset Value
11-8
15
Bit
15
14
13
12
D
When the watchdog timer activates, an internal counter is counting. If this internal count is over the watchdog
D
WRST
R1610C has one independent watchdog timer, which is programmable. The watchdog timer is active
14
RSTFLAG
NMIFLAG
C
Watchdog Timer
C
WRST
Name
Rsvd
ENA
RSTFLAG NMIFLAG
13
®
®
:
R
R
I
I
S
S
C
C
E6h
Watchdog Timer Control Register
C080h
D
D
12
S
Attribute
S
P
P
C
C
R/W
R/W
R/W
R/W
o
o
RO
m
m
m
m
u
u
11
n
n
i
i
c
c
a
a
t
t
i
i
o
o
n
n
Enable Watchdog Timer.
Set 1: Enable Watchdog Timer.
Set 0: Disable Watchdog Timer.
Watchdog Reset.
Set 1: WDT generates a system reset when WDT timeout count is reached.
Set 0: WDT generates an NMI interrupt when WDT timeout count is reached if
Reset Flag.
When watchdog timer reset event has occurred, hardware will set this bit to 1.
This bit will be cleared by any keyed sequence write to this register or external
reset. This bit is 0 after an external reset or 1 after a watchdog timer reset.
NMI Flag.
After WDT generates an NMI interrupt, this bit will be set to 1 by H/W. This bit will
be cleared by any keyed sequence written to this register.
Reserved
10
Rsvd
the NMIFLAG bit is 0. If the NMIFLAG bit is 1, the WDT will generate a
system reset when timeout.
9
8
7
6
Description
5
4
Fast Ethernet RISC Processor
COUNT
3
2
1
R1610C
October 27, 2003
0
Final Version 1.5
Data Sheet