R1610C RDC Semiconductor, R1610C Datasheet - Page 66

• Manufacturer Part Number: R1610C
• Description: High Performance 16 Bits MCU Integrated One 10/100M Mac Controller - 3.3V Operating Voltage/2.5V Core Voltage
• Manufacturer: RDC Semiconductor

R
R
66
Register Offset:
Register Name:
Reset Value
11-6
EN
15
Bit
15
14
13
12
5
4
3
2
D
D
INH_n
14
INH_n
Name
Rsvd
RTG
C
EXT
C
RIU
INT
MC
EN
P
INT
13
®
®
:
Attribute Description
R
R
I
I
S
S
C
C
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
5Eh
Timer 1 Mode/Control Register
0000h
RIU
D
D
12
S
S
P
P
C
C
o
o
m
m
m
m
u
u
11
n
n
0
Enable Bit.
Set 1: The timer 1 is enabled.
Set 0: The timer 1 is inhibited from counting.
The INH_n bit must be set to 1 during writing the EN bit, and the INH_n bit and EN bit
must be in the same write.
Inhibit Bit.
This bit allows selective updating the EN bit. The INH_n bit must be set to 1 during
writing the EN bit, and both the INH_n bit and EN bit must be in the same write. This
bit is not stored and is always read as 0.
Interrupt Bit.
Set 1: An interrupt request is generated when the count register equals a maximum
Set 0: Timer 1 will not issue interrupt request.
Register in Use Bit.
Set 1: The Maxcount Compare B Register of timer 1 is being used.
Set 0: The Maxcount Compare A Register of timer 1 is being used.
Reserved
Maximum Count Bit.
When the timer reaches its maximum count, the MC bit will be set to 1 by H/W. In
dual maxcount mode, this bit is set as each time either Maxcount Compare A or
Maxcount Compare B register is reached. This bit is set regardless of the EN bit
(offset 5Eh [15]).
Re-trigger Bit. This bit defines the control function by the input signal of TMRIN1 pin.
When EXT=1 (5Eh.2), this bit is ignored.
Set 1: Timer1 Count Register (58h) counts internal events; Reset the counting on
Set 0: Low input holds the timer 1 Count Register (58h) value; High input enables the
The definition of setting the (EXT, RTG)
(0, 0) – Timer1 counts the internal events. if the TMRIN1 pin remains high.
(0, 1) – Timer1 counts the internal events; count register resets on every rising
(1, x) – TMRIN1 pin input acts as a clock source and timer1 count register is
Prescaler Bit.
This bit and EXT bit (5Eh [2]) define the timer 1 clock source.
The definition of setting the (EXT, P)
(0, 0) – Timer1 Count Register is incremented by one every 8 internal processor
(0, 1) – Timer1 Count Register is incremented by one which is prescaled by Timer 2.
(1, x) – TMRIN1 pin input acts as a clock source and Timer1 Count Register is
External Clock Bit.
Set 1: Timer 1 clock source from external.
i
i
c
c
a
a
t
t
i
i
o
o
n
n
10
0
count. If the timer is configured in dual max-count mode, an interrupt is
generated each time the count reaches Max-Count A or Max-Count B.
every TMRIN1 input signal going from low to high (rising edge trigger).
counting which counts the internal events.
clocks.
incremented by one every 8 external clocks.
transition on the TMRIN1 pin.
incremented by one every 8 external clocks.
9
0
8
0
7
0
6
0
MC
5
RTG
4
Fast Ethernet RISC Processor
3
P
EXT
2
ALT
1
R1610C
CONT
October 27, 2003
0
Final Version 1.5
Data Sheet