R1610C RDC Semiconductor, R1610C Datasheet - Page 109

• Manufacturer Part Number: R1610C
• Description: High Performance 16 Bits MCU Integrated One 10/100M Mac Controller - 3.3V Operating Voltage/2.5V Core Voltage
• Manufacturer: RDC Semiconductor

R
PS. Update this register only when RCVEN=0
Data Sheet
Final Version 1.5
October 27, 2003
R
20.5
15-13
Register Offset:
Register Name:
Reset Value
12-8 RHPT [4:0]
7-6
5-4
3-2
1-0
15
Bit
D
D
Reserved
14
RXFTH
FIFOTL
TXFTH
C
MBCR: MAC Bus Control Register (08h)
C
Name
Rsvd
Rsvd
[1:0]
[1:0]
[1:0]
13
®
®
:
R
R
I
I
S
S
C
Attribute
C
08h
MBCR: MAC Bus Control Register
1F1Ah
D
D
12
S
S
R/W
R/W
R/W
R/W
P
P
RO
RO
C
C
o
o
m
m
m
m
u
u
11
n
n
i
i
c
c
a
a
t
t
SDRAM Bus Request High Priority Timer.
When MAC issues a bus request to SDRAM arbiter, this timer will start to count
down. After this timer is timeout, if SDRAM arbiter is still not granted to MAC, the
SDRAM bus request will become high priority.
RX FIFO Data Threshold.
MAC receive machine starts to move the received data into host memory when
00: 8 bytes.
01: 16 bytes. (Default)
10: 32 bytes.
FIFO Transfer Length.
The every transfer data length between MAC FIFO and SDRAM.
00: 4 bytes.
01: 8 bytes.
10: 16 bytes. (Default)
Reserved
Wait time = 0 ~15 host clocks. (Default=15 host clocks)
Reserved
receiving data over the RX FIFO threshold.
11: 64 bytes.
TX FIFO Data Threshold.
MAC transmit machine starts to send out packets to PHY when transmitting data
into TX FIFO over the threshold.
00: 16 bytes.
01: 32 bytes.
10: 64 bytes. (Default)
11: 96 bytes.
11: 32 bytes.
i
i
o
o
RHPT [4:0]
n
n
10
9
8
Reserved
7
6
Description
RXFTH [1:0]
5
4
Fast Ethernet RISC Processor
TXFTH [1:0]
3
2
FIFOTL [1:0]
1
R1610C
0
109