R1610C RDC Semiconductor, R1610C Datasheet - Page 11

• Manufacturer Part Number: R1610C
• Description: High Performance 16 Bits MCU Integrated One 10/100M Mac Controller - 3.3V Operating Voltage/2.5V Core Voltage
• Manufacturer: RDC Semiconductor

R
Data Sheet
Final Version 1.5
October 27, 2003
R
Chip Select Unit Interface
PIN No.
124
D
D
43
44
46
47
48
49
50
51
66
80
67
68
69
70
71
72
76
77
78
79
95
94
93
92
90
89
88
87
61
60
58
57
56
54
53
52
96
C
C
®
®
A17/ PIO7/SAD6
A18/PIO8/SAD7
A19/PIO9/ALE
PCS5_n/PIO3
R
R
I
I
S
S
A16/SAD5
A15/SAD4
A14/SAD3
A13/SAD2
A12/SAD1
A10/MA10
A11/SAD0
C
C
Symbol
A9/MA9
A8/MA8
A7/MA7
A6/MA6
A5/MA5
A3/MA3
A2/MA2
A1/MA1
A0/MA0
D
D
A4MA4
UCS_n
S
S
P
P
D10
D12
D13
D14
D15
D11
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
C
C
o
o
m
m
m
m
u
u
n
n
i
i
c
c
a
a
t
t
i
i
o
o
n
n
I/O/PU*
O/PU
Type
I/O
I/O
Address bus. Non-multiplexed memory or I/O addresses. The
address bus is one-half of a SD_CLK period earlier than the D
bus. The address bus is in a high-impedance state during a bus
hold or reset.
SAD [7:0]: The combination pins with addresses and data. They
are designed for slower peripheral bus.
ALE: Address latch enable. Active high. This pin indicates an
address output on the D bus. Address is guaranteed to be valid
on the trailing edge of ALE.
MA [10:0]: The SDRAM raw and column address output.
Data bus for memory or I/O access.
The D bus is in a floating state during a bus hold or reset
condition and this bus can also be used to load system
configuration information (with pull-up or pull-low resistor) into
the RESCON register when RST_n goes from low to high and
the Watchdog timeout is reset.
Upper memory chip select. For UCS_n, this pin is active low
when the system accesses the defined portion of memory block
for the upper 512K bytes (80000h-FFFFFh) memory region.
UCS_n defaulted active address region is from F0000h to
FFFFFh after power-on reset. The address range for UCS_n is
programmed by software. This pin incorporates a weak pull-up
resistor.
Peripheral chip selects/latched address bit. For PCS_n feature,
these pins are active low when the micro-controller accesses
the fifth or sixth region of the peripheral memory (I/O or memory
space) The base address of PCS n is programmable These
Fast Ethernet RISC Processor
Description
R1610C
11