R1610C RDC Semiconductor, R1610C Datasheet - Page 36

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R1610C

Manufacturer Part Number
R1610C
Description
High Performance 16 Bits MCU Integrated One 10/100M Mac Controller - 3.3V Operating Voltage/2.5V Core Voltage
Manufacturer
RDC Semiconductor
Datasheet
R
R
10.4
avoid wait states, ARDY must be high within a specified setup time prior to phase 2 of T1 and keep to phase 2 of
T2. To insert wait states, ARDY must be driven low within a specified setup time prior to phase 2 of T1 or phase 2
of T2. When the SDRAMEN bit in the SDRAM Control Register (FEF4h) is set to 1, the external ready ARDY and
internal wait states are ignored while accessing the SDRAMs.
36
D
D
Wait states extend the data phase of the bus cycle. The ARDY input with low level will insert wait states. To
C
Wait States
C
®
®
ARDY(Normally Not-Ready System)
R
R
I
I
S
S
C
C
D
D
S
S
(Normally
P
P
System)
C
SD_CLK
C
ARDY
Ready
o
o
m
m
m
m
u
u
n
n
i
i
c
c
a
a
t
t
i
i
o
o
n
n
SD_CLK
Asynchronous Ready Waveforms
Case 1
Case 2
Case 3
Case 4
T1
Asynchronous Ready Waveforms
T2
TW
T3
T2
T1
T3
TW
TW
T3
T2
TW
TW
TW
TW
T3
Fast Ethernet RISC Processor
T4
T4
T4
T4
T4
R1610C
October 27, 2003
Final Version 1.5
Data Sheet

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