R1610C RDC Semiconductor, R1610C Datasheet - Page 39

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R1610C

Manufacturer Part Number
R1610C
Description
High Performance 16 Bits MCU Integrated One 10/100M Mac Controller - 3.3V Operating Voltage/2.5V Core Voltage
Manufacturer
RDC Semiconductor
Datasheet
R
A8h registers. The base address memory block can be located anywhere within the 1M bytes memory space,
exclusive of the areas associated with the SDRAM space and UCS_n. If the chip selects are mapped to I/O space,
the access range is 64k bytes. PCS5_n can be configured from (0 to 31wait states) + (1 to 225 wait states).
PCS3_n – PCS0_n can be configured from (1 to 31 wait states) + (1 to 225 wait states). The PCSx_n pins are not
active on reset. The PCSx_n pins are activated as chip selects by writing to the peripheral chip select register 0
and 1.
Data Sheet
Final Version 1.5
October 27, 2003
R
11.2
Register Offset:
Register Name:
Reset Value
15-8 BA[19:12]
7-4
1-0
15
Bit
3
2
D
D
14
In order to define these pins, the peripheral or memory chip selects are programmed through A4h and
Name
R[1:0]
C
PCSx_n
Rsvd
C
R3
R2
13
®
®
:
R
R
Attribute
I
I
S
S
C
C
A4h
Peripheral Chip Select Register 0
----
R/W
R/W
R/W
R/W
D
D
12
RO
BA[19:12]
S
S
P
P
C
C
o
o
m
m
m
m
u
u
11
n
n
Base Address. BA[19:12] corresponds to Bit [19:12] of the 1M-Byte (20-bits)
programmable base address of the PCS_n chip select block. When the PCS_n chip
selects are mapped to I/O space, BA[19:16] must be written to 0000b because the
I/O address bus is only 64K bytes (16 bits) wide.
Please refer to the following table for register FFAAh bit[8:6].
Reserved
Ready Mode. This bit is configured to enable/disable the ready mode for the
PCS3_n – PCS0_n chip selects.
Bit 3, Bit 1-0: R3, R1, R0, Wait-State Values.
PR4 (refer to Bit 5 in the A8h register), R3, R1, and R0 determine the number of wait
states inserted into T3 of the PCS3_n – PCS0_n access.
See Bit[1:0].
Set 1: external ready is ignored. Set 0: external ready is required.
i
i
c
c
0,
0,
1,
1,
1,
1,
a
a
t
t
i
i
o
o
n
n
10
1,
1,
0,
0,
1,
1,
PR4, R3, R1, R0
0,
0,
0,
0,
0
1
0
1
0
1
9
0,
--
--
--
--
--
--
0,
0,
0,
8
0,
0,
1,
1,
2
3
5
7
9
15
7
0
0
1
0
1
6
0
--
--
--
--
-- Wait States
Description
5
0
1
3
5
7
4
0
Fast Ethernet RISC Processor
R3
3
R2
2
R1
1
R1610C
R0
0
39

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