R1610C RDC Semiconductor, R1610C Datasheet - Page 12

• Manufacturer Part Number: R1610C
• Description: High Performance 16 Bits MCU Integrated One 10/100M Mac Controller - 3.3V Operating Voltage/2.5V Core Voltage
• Manufacturer: RDC Semiconductor

R
R
Interrupt Control Unit Interface
Timer Control Unit Interface
12
PIN No.
PIN No.
125
126
D
34
35
10
D
4
5
6
8
9
C
C
PCS3_n/PIO26/IOW_n
PCS2_n/PIO25/IOR_n
®
®
PCS1_n/PIO15
PCS0_n/PIO14
TMRIN0/PIO11
TMRIN1/PIO0
R
R
I
I
INT2/PIO31
S
S
C
C
Symbol
Symbol
D
D
S
S
INT1
INT0
P
P
NMI
C
C
o
o
m
m
m
m
u
u
n
n
i
i
c
c
a
a
t
t
i
i
o
o
n
n
I/O/PU*
I/O/PU*
I/O/PU*
I/O/PU*
Type
Type
I/PD
I/PD
I/PD
pins are asserted with the multiplexed D address bus and do not
float during bus hold conditions.
Peripheral chip selects. These pins are active low when the
microcontroller accesses the defined peripheral memory block
(I/O or memory address). For I/O access, the base address can
be programmed in the region from 00000h to 0FFFFh. For
memory address access, the base address can be located in
the 1M-Byte memory address region. These pins are asserted
with the multiplexed D address bus and do not float during bus
holds.
Peripheral chip selects. These pins are active low when the
microcontroller accesses the defined peripheral memory block
(I/O or memory address). For I/O access, the base address can
be programmed in the region from 00000h to 0FFFFh.
memory address access, the base address can be located in
the 1M-Byte memory address region. These pins are asserted
with the multiplexed D address bus and do not float during bus
holds.
When register FFEAh bit6 is set, PIN34 is IOR_n and PIN35 is
IOW_n.
IOR_n/IOW_n are for PCMCIA bus.
Nonmaskable Interrupt. The NMI is the highest priority hardware
interrupt and is nonmaskable. When this pin is asserted (NMI
transition from low to high), the microcontroller always transfers
the address bus to the location specified by the nonmaskable
interrupt vector in the micro controller interrupt vector table. The
NMI pin must be asserted for at least one SD_CLK period to
guarantee that the interrupt is recognized.
Maskable Interrupt Request 2.
INT2, it’s active high. The interrupt input can be configured to be
either edge-triggered or level-triggered. The requesting device
must hold the INT2 until the request is acknowledged to
guarantee interrupt recognition.
Maskable Interrupt Request 1.
INT1, except the differences in the interrupt line and interrupt
address vector, the function of INT1 is the same as that of INT2.
Maskable interrupt request 0.
INT0, except the differences in the interrupt line and interrupt
address vector, the function of INT0 is the same as that of INT2.
Timer input. These pins can be used as clock or control signal
input, depending upon the programmed timer mode. After
internally synchronizing low to high transitions on TMRIN, the
timer controller increments. These pins must be pulled up if
not being used.
Description
Description
Fast Ethernet RISC Processor
R1610C
October 27, 2003
Final Version 1.5
Data Sheet
For