R1610C RDC Semiconductor, R1610C Datasheet - Page 77

• Manufacturer Part Number: R1610C
• Description: High Performance 16 Bits MCU Integrated One 10/100M Mac Controller - 3.3V Operating Voltage/2.5V Core Voltage
• Manufacturer: RDC Semiconductor

R
only). This register is used to enable the FIFO, clear the FIFO, set the RCVR FIFO trigger level, and select the type
of DMA signaling.
Data Sheet
Final Version 1.5
October 27, 2003
R
16.5
Register Offset:
Register Name:
Reset Value
10-8
7-6
5-4
15
Bit
0
3
D
D
The FIFO Control Register (write only) is at the same location as the Interrupt Identification Register (read
DMACTL
RCVRTL
14
0
Select
Name
Mode
Rsvd
C
DMA
FIFO Control Register
C
[2:0]
[1:0]
0
13
®
®
:
Attribute
R
R
I
I
0
S
S
C
C
R/W
R/W
R/W
84h
UART0 FIFO Control Register (Write Only)
X000h
RO
D
D
12
S
S
Fourth
P
P
C
C
o
o
m
m
m
m
u
u
11
n
n
With the DMA transfers listed as follows, users can configure these bits for the UART
Port.
RCVR Trigger.
These two bits are used to set the trigger level for the RCVR FIFO interrupt.
Reserved
DMA Mode Select.
Setting FCR0[3]=1 will cause the UART to change from mode 0 to mode 1 if
FCR0[0]=0.
i
i
c
c
a
a
t
t
i
i
o
o
n
n
MODEM Status
10
DMACTL [2:0]
RCVRTL1-0 – RCVR FIFO Trigger Level (Bytes)
0 0
0 1
1 0
1 1
9
DMACTL [2:0]
-- 01 Bytes
-- 04 Bytes
-- 08 Bytes
-- 14 Bytes
000
001
010
011
100
101
110
111
8
Trigger
RCVR
(MSB)
7
clear to send, data set ready,
ring indicator, or data carrier
detect
Trigger
RCVR
(LSB)
6
No DMA
Receive
Reserved
No DMA
No DMA
DMA0
DMA1
DMA0
DMA1
Description
5
Rsvd
4
Fast Ethernet RISC Processor
Select
Mode
DMA
DMA1
DMA0
Transmit
No DMA
Reserved
No DMA
No DMA
DMA1
DMA0
3
Reset
XMIT
FIFO
transmitter holding
register
reading the
modem status
register
2
RCVR
Reset
FIFO
1
R1610C
Enabled
FIFO
0
77