R1610C RDC Semiconductor, R1610C Datasheet - Page 53

• Manufacturer Part Number: R1610C
• Description: High Performance 16 Bits MCU Integrated One 10/100M Mac Controller - 3.3V Operating Voltage/2.5V Core Voltage
• Manufacturer: RDC Semiconductor

R
be read without affecting the current interrupt requests.
Data Sheet
Final Version 1.5
October 27, 2003
R
15-11
IREQ
Register Offset:
Register Name:
Reset Value
Register Offset:
Register Name:
Reset Value
14-5
7-4
3-2
4-0
15
Bit
15
Bit
10
15
9
8
1
0
D
D
14
D1/I6 –
14
The Poll Status (POLLST) register mirrors the current state of the Poll register. The POLLST register can
Name
Name
S[4:0]
IREQ
D0/I5
Rsvd
MAC
I[3:0]
Rsvd
Rsvd
TMR
SP0
SP1
C
C
Reserved
13
13
®
®
:
:
Attribute
Attribute
R
R
I
I
S
S
C
C
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
28h
Interrupt Mask Register
FFFFh
26h
Poll Status Register
──
D
D
12
12
S
S
P
P
C
C
o
o
m
m
m
m
u
u
11
11
n
n
Reserved
Serial Port 0 Interrupt Mask.
When set 1, this bit indicates that the asynchronous serial port 0 interrupt is masked.
Serial Port 1 Interrupt Mask.
When set 1, this bit indicates that the asynchronous serial port 1 interrupt is masked.
MAC Interrupt Mask.
When set 1, this bit indicates that the MAC interrupt is masked.
External Interrupt Mask.
When set 1, I3-I0 bits indicate that the corresponding interrupts are masked.
DMA Channel or INT Interrupt Masks.
When set 1, these bits indicate that the corresponding interrupts are masked.
Reserved
Timer Interrupt Mask.
When set 1, this bit indicates that the Timer controller interrupt is masked.
Interrupt Request.
Set 1: if an interrupt is pending. The S[4:0] field contains valid data.
Reserved
Poll Status.
It indicates the interrupt type of the highest priority pending interrupts.
i
i
c
c
a
a
t
t
i
i
o
o
n
n
SP0
10
10
Reserved
SP1
9
9
MAC
8
8
I3
7
7
I2
6
6
Description
Description
I1
5
5
I0
4
4
Fast Ethernet RISC Processor
D1/I6
3
3
S [4:0]
D0/I5
2
2
Rsvd
1
1
R1610C
TMR
0
0
53