R1610C RDC Semiconductor, R1610C Datasheet - Page 72

• Manufacturer Part Number: R1610C
• Description: High Performance 16 Bits MCU Integrated One 10/100M Mac Controller - 3.3V Operating Voltage/2.5V Core Voltage
• Manufacturer: RDC Semiconductor

R
16.
CPU. These registers control the UART operation in which the transmission and reception of data and status are
included, and each register bit in the Table has its own name.
R
72
Note: These bits are always 0 in the 16450 mode.
Register
Address
8Ch/1Ch
8Ah/1Ah
8Eh/1Eh
80h/10h
82h/12h
84h/14h
86h/16h
88h/18h
D
16550 UART Serial Port
D
The system programmer may access any of the UART registers summarized in the following Table via the
C
C
Latch(LS)
Latch(MS
Transmitt
Register
Identified
Receiver
MODEM
MODEM
Register
Register
Interrupt
Register
Interrupt
Register
Register
Register
Register
Register
Register
Register
Holding
Scratch
Enable
Control
Control
Control
Divisor
Divisor
Status
Status
Name
Buffer
FIFO
Line
Line
er
)
®
®
R
R
I
I
S
S
C
C
Mnem.
D
D
MCR
MSR
RBR
THR
DLM
FCR
LCR
SCR
DLL
LSR
S
IER
S
IIR
P
P
C
C
o
o
m
m
m
m
u
u
DMACT
n
n
i
i
L[2:0]
c
c
15-8
a
a
t
t
i
i
o
0
0
0
0
0
0
0
0
0
0
0
o
n
n
Enabled
Error in
RBR[7] RBR[6]
THR[7] THR[6]
SCR[7] SCR[6]
Trigger
DL[15]
(Note)
RCVR
(MSB)
RCVR
(Note)
DLAB
DL[7]
FIFO
Level
FIFO
DCD
7
0
0
Enabled
Trigger
DL[14]
RCVR
(Note)
TEMT
(LSB)
DL[6]
Level
FIFO
SB
RI
6
0
0
Reserved Reserved
RBR[5]
THR[5]
SCR[5]
DL[13]
THRE
DL[4]
ACE
DSR
SP
5
0
0
Bit No.
RBR[4] RBR[3] RBR[2] RBR[1] RBR[0]
SCR[4] SCR[3] SCR[2] SCR[1] SCR[0]
THR[4] THR[3] THR[2] THR[1] THR[0]
DL[12]
DL[4]
Loop
EPS
CTS
BI
4
0
0
DDCD
DL[11] DL[10] DL[9]
Select
LDCD
DL[3]
EMSI ERLSI
Mode
IID[2]
DMA
PEN
FE
3
Fast Ethernet RISC Processor
Reset
DL[2]
IID[1]
XMIT
FIFO
TERI
STB WLS[1] WLS[0]
LRI
PE
2
RCVR
DDSR DCTS
ETHR
Reset
DL[1]
IID[0]
FIFO
RTS
OE
EI
1
Enable
ERDAI
DL[0]
DL[8]
FIFO
DTR
DR
IP
0
d
R1610C
October 27, 2003
Final Version 1.5
Read Only
Write Only
DLAB=0
DLAB=0
DLAB=1
DLAB=0
DLAB=1
& write
& read
Note.
only
only
Data Sheet