R1610C RDC Semiconductor, R1610C Datasheet - Page 42

• Manufacturer Part Number: R1610C
• Description: High Performance 16 Bits MCU Integrated One 10/100M Mac Controller - 3.3V Operating Voltage/2.5V Core Voltage
• Manufacturer: RDC Semiconductor

R
12.
R
generates a memory read request to the bus interface unit.
A user guide to program SDRAM:
(1) Configure Lower Memory Chip Select Register (A2h) to set SDRAM space. The suggestion value is 7F38h.
(2) Set Clock Prescaler Register (E2h) and enable RCU Register (E4h) to enable SDRAM refresh.
14-0 RC[14:0]
14-0
42
Register Offset:
Register Name:
Reset Value
Register Offset:
Register Name:
Reset Value
15
Bit
15
Bit
15
15
E
0
D
Refresh Control UNIT
D
The Refresh Control Unit (RCU) automatically generates refresh bus cycle. After a period of time, the RCU
14
14
T[14:0]
Name
Name
Rsvd
C
C
E
13
13
®
®
:
:
Attribute
R
Attribute
R
I
I
S
S
C
C
RW
RO
E2h
Clock Prescaler Register
0080h
RW
E4h
Enable RCU Register
8000h
RO
D
D
12
12
S
S
P
P
C
C
o
o
m
m
m
m
u
u
11
11
n
n
Reserved
Refresh Counter Reload Value. It contains the value of the desired clock count
interval between refresh cycles. The counter value should not be set to less than 12h,
otherwise there would never be sufficient bus cycle available for the processor to
execute code.
For Example: SDRAM specification specifies to refresh 1 time every 15.6 u sec and
system clock is 25Mhz.
The Refresh Counter Reload Value = 15.6us*25Mhz = 15.6us / 40ns = 390.
Enable RCU
Set 1: Enable the refresh counter unit.
Set 0: Clear the refresh counter and stop refresh requests, but will not reset the
refresh address.
Refresh Count. This read-only field contains the present value of the down counter
which triggers refresh requests.
i
i
c
c
a
a
t
t
i
i
o
o
n
n
10
10
9
9
8
8
RC[14:0]
T[14:0]
7
7
6
6
Description
Description
5
5
4
4
Fast Ethernet RISC Processor
3
3
2
2
1
1
R1610C
October 27, 2003
0
0
Final Version 1.5
Data Sheet