R1610C RDC Semiconductor, R1610C Datasheet - Page 117

• Manufacturer Part Number: R1610C
• Description: High Performance 16 Bits MCU Integrated One 10/100M Mac Controller - 3.3V Operating Voltage/2.5V Core Voltage
• Manufacturer: RDC Semiconductor

R
register is set to 1. Reading the Event Counter register will clear the corresponding bits. Those event counters will
Data Sheet
Final Version 1.5
October 27, 2003
R
20.20
20.21
15-10
Register Offset:
Register Name:
Reset Value
Register Offset:
Register Name:
Reset Value
6-5
15
Bit
15
9
8
7
4
3
2
1
0
The correspond bit in Event Counter INT status register will be set when the MSB bit in related Event Counter
D
D
14
14
Reserved
C
MIER: INT Enable Register (40h)
MECISR: Event Counter INT Status Register(44h)
C
ECNTOE
RXDNAE
RXENDE
TXENDE
MCHGE
TXEIEN
RXFFE
RXEIE
Name
Rsvd
Rsvd
13
13
®
®
:
:
Reserved
R
R
I
I
S
S
C
C
40h
MIER: INT Enable Register
0000h
44h
MECISR: Event Counter INT Status Register
0000h
D
D
12
12
S
S
P
P
Attribute
C
C
o
o
m
m
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RW
m
RO
RO
m
TDPCI
u
u
11
11
n
n
i
i
c
c
a
a
t
t
i
i
o
o
n
n
LCCI
Reserved.
PHY Link Changed Interrupt Enable
Set 1: Enable MAC to generate interrupts to CPU.
Event Counter Overflow Interrupt Enable.
Set 1: Enable MAC to generate interrupts to CPU.
TX Early Interrupt Enable.
Set 1: Enable MAC to generate interrupts to CPU.
Reserved.
Transmit Packet Finish Interrupt Enable.
Set 1: Enable MAC to generate interrupts to CPU.
RX Early Interrupt Enable.
Set 1: Enable MAC to generate interrupts to CPU.
RX FIFO Full Interrupt Enable.
Set 1: Enable MAC to generate interrupts to CPU.
RX Descriptor Unavailable Interrupt Enable.
Set 1: Enable MAC to generate interrupts to CPU.
Receive Packet Finish Interrupt Enable.
Set 1: Enable MAC to generate interrupts to CPU.
10
10
MCHGE
STPCI
9
9
ECNTO
RFFCI
E
8
8
TXEIEN
RDUCI
7
7
Rsvd
6
6
Reserved
LONGCI RUNTCI CRCECI BCCI
Description
5
5
TXENDE RXEIE RXFFE
4
4
Fast Ethernet RISC Processor
3
3
2
2
RXDNA
MCCI
1
E
1
R1610C
RXEND
SRPCI
0
E
0
117