R1610C RDC Semiconductor, R1610C Datasheet - Page 85

• Manufacturer Part Number: R1610C
• Description: High Performance 16 Bits MCU Integrated One 10/100M Mac Controller - 3.3V Operating Voltage/2.5V Core Voltage
• Manufacturer: RDC Semiconductor

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occur as follows:
A. The transmitter holding register interrupt (02) occurs when the XMIT FIFO is empty; it is cleared as soon as the
B. The transmitter FIFO empty indications will be delayed 1 character time minus the last stop bit time whenever
Mode of operation. Since the RCVR and XMITTER are controlled separately, either one or both can be in the polled
mode of operation. In this mode, the user’s program will check RCVR and XMITTER status via the LSR. As stated
previously:
RCVR and XMIT FIFOs are still fully capable of holding characters.
Data Sheet
Final Version 1.5
October 27, 2003
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16.13
transmitter holding register is written to (1 to 16 characters may be written to the XMIT FIFO while servicing this
interrupt) or the IIR is read.
the following occurs: THRE=1 and there have not been at least two bytes at the same time in the transmit FIFO,
since the last THRE=1. The first transmitter interrupt after changing FCR0 will be immediate, if it is enabled.
Character timeout and RCVR FIFO trigger level interrupts have the same priority as the current received data
available interrupt; XMIT FIFO empty has the same priority as the current transmitter holding register empty
interrupt.
LSR [0] will be set as long as there is one byte in the RCVR FIFO.
LSR [1] to LSR [4] will specify which error(s) has occurred.
Character error status is handled the same way as in the interrupt mode, the IIR is not affected since IER2=0.
LSR [5] will indicate when the XMIT FIFO is empty.
LSR [6] will indicate that both the XMIT FIFO and Shift Register are empty.
LSR [7] will indicate whether there are any errors in the RCVR FIFO.
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When the XMIT FIFO and transmitter interrupts are enabled (FCR [0]=1, IER [1]=1), XMIT interrupts will
With FCR [0]=1, resetting IER [0], IER [1], IER [2], IER [3] or all to zero puts the UART in the FIFO Polled
There is no trigger level reached or timeout condition indicated in the FIFO Polled Mode, however, the
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FIFO Polled Mode Operation
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Fast Ethernet RISC Processor
R1610C
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