R1610C RDC Semiconductor, R1610C Datasheet - Page 76

• Manufacturer Part Number: R1610C
• Description: High Performance 16 Bits MCU Integrated One 10/100M Mac Controller - 3.3V Operating Voltage/2.5V Core Voltage
• Manufacturer: RDC Semiconductor

R
Interrupt Control Function:
R
Mode
FIFO
Only
Bit 3
76
Register Offset:
Register Name:
Reset Value
7-6
5-4
2-1
15
Bit
0
0
0
1
0
3
0
D
D
Identification
Bit
Enabled
14
2
0
1
1
1
0
IID[1:0]
Name
FIFOs
Rsvd
C
Interrupt
Register
C
IID2
IP
Bit
1
0
1
0
0
1
13
®
®
:
R
R
Bit
Attribute
I
I
0
1
0
0
0
0
S
S
C
C
84h
UART0 Interrupt Ident. Register (Read Only)
XX01h
R/W
R/W
R/W
R/W
D
D
RO
12
S
S
Highest Receiver Line Status overrun error, parity error,
Second Received Data
Second Character Timeout
Third
P
P
Priority
C
C
Level
o
─
o
m
m
m
m
u
u
11
n
n
i
i
These two bits are set when FCR [0]=1.
Reserved and always 0.
The Interrupt ID indicator.
In the NS16450 Mode, this bit is 0. In the FIFO mode, this bit is set along with bit 2
when a timeout interrupt is pending.
The Interrupt ID indicator.
These two bits are used to identify the highest priority interrupt pending as indicated
in the following table:
The Interrupt Pending indicator.
This bit can be used in a prioritized interrupt environment to indicate whether an
c
c
interrupt is pending or not.
Set 1: Indicate that no interrupt is pending.
Set 0: Indicate that an interrupt is pending and the IIR contents may be used as a
a
a
t
t
i
i
o
o
n
n
None
Available
Indication
Transmitter Holding
Register Empty
10
Interrupt Type
pointer to the appropriate interrupt service routine.
9
Interrupt Set and Reset Functions
8
Enabled
FIFOs
7
none
framing error, or break
interrupt
received data available or
trigger level reached
no character has been
removed from or input to the
RCVR FIFO during the last 4
characters times and there is
at least 1 character in it during
this time
transmitter holding
register empty
Enabled
FIFOs
6
Interrupt Source
Description
5
0
4
0
Fast Ethernet RISC Processor
IID2
3
IID1
reading the line
status register
reading the
receiver buffer
register or the
FIFO dropping
below the trigger
level
reading the
receiver buffer
register
reading the IIR
register (if the
source of interrupt
is available) or
writing into the
2
Interrupt Rest
Control
─
IID0
1
R1610C
October 27, 2003
IP
0
Final Version 1.5
Data Sheet