R1610C RDC Semiconductor, R1610C Datasheet - Page 80

• Manufacturer Part Number: R1610C
• Description: High Performance 16 Bits MCU Integrated One 10/100M Mac Controller - 3.3V Operating Voltage/2.5V Core Voltage
• Manufacturer: RDC Semiconductor

R
each Bit of the Line Status Register are described as below.
R
16.8
80
15-5
Register Offset:
Register Name:
Reset Value
3, 2
Bit
15
Bit
5
4
1
0
D
D
This register provides status information to the part of the CPU processing data transfer. The contents of
14
LDCD,
Name
Name
Rsvd
Loop
ACE
DTR
RTS
C
Line Status Register
C
LRI
13
®
®
:
Attribute
Attribute
R
R
I
I
S
S
C
C
R/W
R/W
R/W
R/W
RW
RO
8Ah
UART0 Line Status Register
XX60h
D
D
12
S
S
P
P
C
C
o
o
m
m
m
m
u
u
11
n
n
Reserved and always 0.
Autoflow Control is Enabled when set.
ACE can be configured by MCR bits 1and 5 as shown in the following table.
This bit provides a local loop back feature for diagnostic testing of the UART.
Set to 1, the following occur:
The transmitter Serial Output (SOUT) is set to the Marking (logic 1) state. The
receiver Serial Input (SIN) is disconnected. The output of the Transmitter Shift
Register is “looped back” into the Receiver Shift Register input. The four MODEM
Control inputs (CTS_n, DSR_n, RI_n, and DCD_n) are disconnected, and the 2
MODEM Control outputs (DTR_n and RTS_n) are internally connected to the two
MODEM Control inputs (DSR_n, CTS_n), and the MODEM Control output pins are
forced to their inactive state (high).
In the diagnostic mode, data transmitted are immediately received. This feature
allows the processor to verify the transmitted and received data paths of the UART.
In the diagnostic mode, the receiver and transmitter interrupts are fully operational.
The MODEM Control Interrupts are also operational, but the sources of the interrupts
are now the lower four bits of the MODEM Control Register instead of the four
MODEM Control inputs. The interrupts are still controlled by the Interrupt Enable
Register.
Bit3: The bit controls DCD_n signal internal if loopback mode is enabled.
Bit2: The bit controls RI_n signal internal if loopback mode is enabled.
The Request To Send bit. This bit controls the Request To Send (RTS_n) output.
Set 1: the RTS_n output is forced to logic 0.
Set 0: the RTS_n output is forced to logic 1.
The Data Terminal Ready indicator. This bit controls the Data Terminal Ready
(DTR_n) output.
Set 1: the DTR_n output is forced to logic 0.
Set 0: the DTR_n output is forced to logic 1.
Note: The DTR_n output of the UART may be applied to an EIA inverting line driver
i
i
c
c
a
a
t
t
i
i
o
o
n
n
(such as the DS1488) to obtain the proper polarity input at the succeeding
MODEM or data set.
10
9
8
(Note 2)
Error in
RCVR
7
TEMT THRE
6
Description
Description
5
BI
4
Fast Ethernet RISC Processor
FE
3
PE
2
OE
1
R1610C
October 27, 2003
DR
0
Final Version 1.5
Data Sheet