R1610C RDC Semiconductor, R1610C Datasheet - Page 55

• Manufacturer Part Number: R1610C
• Description: High Performance 16 Bits MCU Integrated One 10/100M Mac Controller - 3.3V Operating Voltage/2.5V Core Voltage
• Manufacturer: RDC Semiconductor

R
14.
of the CPU. There are two DMA channels in the DMA unit. Each channel can accept DMA requests from one of
three sources: external pins (DRQ0 for channel 0 or DRQ1 for channel 1), serial ports (port 0 or port 1), or Timer 2
overflow. The data transfer from sources to destinations can be memory to memory, memory to I/O, I/O to I/O, or
I/O to memory. Either bytes or words can be transferred to or from even or odd addresses and two bus cycles are
necessary (read from sources and write to destinations) for each data transfer.
cannot be separated by a bus hold request, a refresh request, or another DMA request. The registers (CAh, C8h,
C6h, C4h, C2h, C0h, DAh, D8h, D6h, D4h, D2h, and D0h) are used to configure and operate the two DMA
channels.
Data Sheet
Final Version 1.5
October 27, 2003
R
14.1
D
DMA UNIT
D
The DMA controller provides the data transfer between the memory and peripherals without the intervention
Every DMA transfer consists of two bus cycles (see figure of Typical DMA Transfer) and the two bus cycles
C6h,C4h-Destination Address Channel 0
D6h,D4h-Destination Address Channel 1
C2h,C0h-Source Address Channel 0
D2h,D0h-Source Address Channel 1
C
DMA Operation
C
C8h-Transfer Counter Channel 0
D8h-Transfer Counter Channel 1
20-bit Adder/Subtractor
®
®
R
R
I
I
S
S
C
C
D
D
S
S
P
P
C
C
20 bit
o
20 bit
o
m
m
m
m
u
u
n
n
Internal Address/Data Bus
i
i
c
c
a
a
t
t
i
i
o
o
n
n
Channel Control Register0,CAh
Channel Control Register1,DAh
Adder Control
Logic
Control
DMA
Logic
DMA Unit Block
16 bit
Arbitration
Request
Logic
INT
Fast Ethernet RISC Processor
CAh.8-Channel 0
DAh.8-Channel 1
TDRQ
Interrupt Request
CAH.4-Channel 0
DAH.4-Channel 1
R1610C
Timer 2 Request
DRQ0
DRQ1
Serial Port0
Serial Port1
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