R1610C RDC Semiconductor, R1610C Datasheet - Page 81

• Manufacturer Part Number: R1610C
• Description: High Performance 16 Bits MCU Integrated One 10/100M Mac Controller - 3.3V Operating Voltage/2.5V Core Voltage
• Manufacturer: RDC Semiconductor

R
Data Sheet
Final Version 1.5
October 27, 2003
R
7
6
5
4
3
2
D
D
(Note 2)
Error in
RCVR
TEMT
THRE
C
C
PE
FE
BI
®
®
R
R
I
I
S
S
C
C
R/W
R/W
R/W
R/W
R/W
R/W
D
D
S
S
P
P
C
C
o
o
m
m
m
m
u
u
n
n
Error in Receive FIFO.
In the NS16450 Mode, this is a 0. In the FIFO mode, LSR [7] is set to 1 when there is
Note: The Line Status Register is intended for read operations only. Writing to this
The Transmitter Empty indicator.
Set 1: This bit is set to 1 whenever the Transmitter Holding Register (THR) and the
Set 0: This bit is reset to 0 whenever either the Transmitter Holding Register or the
In the FIFO mode, this bit is set to one whenever the transmitter FIFO and shift
register are both empty.
The Transmitter Holding Register Empty indicator.
This bit indicates that the UART is ready to accept a new character for transmission.
In the FIFO mode, this bit is set when the XMIT FIFO is empty; it is cleared when at
Break Interrupt indicator.
In the FIFO mode, this error is associated with the particular character in the FIFO it
applies to. This error is revealed to the CPU when its associated character is at the
top of the FIFO. When break occurs, only one zero character is loaded into the FIFO.
The next character transfer is enabled after SIN goes to the marking state and
receives the next valid start bit.
Note: Bits 1 through 4 are the error conditions that produce a Receiver Line Status
Framing Error indicator.
This bit indicates that the received characters don’t have a valid Stop Bit.
Set 1: This bit will be set to 1 whenever the Stop Bit follows the last data bit or Parity
Set 0: Automatic set to 0 whenever the CPU reads the contents of the Line Status
In the FIFO mode, this error is associated with the particular character in the FIFO it
applies to. This error is revealed to the CPU when its associated character is at the
top of the FIFO. The UART will try to resynchronize after a framing error occurs. To
do this, it assumes that the framing error was due to the next start bit, so it samples
this “start” bit twice and then takes in the “data”.
Parity Error indicator.
This bit indicates that the received data character does not have the correct even or
at least one parity error, framing error or break indication in the FIFO. LSR [7] is
cleared when the CPU reads the LSR, if there are no subsequent errors in the FIFO.
In addition, this bit causes the UART to issue an interrupt to the CPU when the
Transmit Holding Register Empty Interrupt Enable is set high.
Set 1: This bit will be set to 1 when a character is transferred from the Transmitter
Set 0: This bit is reset to 0 upon the CPU loading character to the Transmitter Holding
least 1 byte is written to the XMIT FIFO.
Set 1: This bit will be set to 1 whenever the received data input is held in the Spacing
Set 0: This bit will be reset whenever the CPU reads the contents of the Line Status
odd parity, as selected by the even-parity select bit.
Set 1: This bit will be set upon detection of a parity error.
Set 0: Automatic set to 0 whenever the CPU reads the contents of the Line Status
i
i
c
c
a
a
t
t
i
i
o
o
n
n
interrupt whenever any of the corresponding conditions are detected and the
interrupt is enabled.
Transmitter Shift Register (TSR) are both empty.
Transmitter Shift Register contains a data character.
Holding Register into the Transmitter Shift Register.
Register.
(logic 0) state for longer than a full word transmission time (that is, the total
time of Start Bit + Data Bits + Parity Bit + Stop Bit).
Register.
bit is detected as a logic 0 bit (Spacing level).
Register.
register is not recommended as this operation is only used for factory testing.
Fast Ethernet RISC Processor
R1610C
81